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PDF HI5702 Data sheet ( Hoja de datos )
| Número de pieza | HI5702 | |
| Descripción | 40 MSPS A/D Converter | |
| Fabricantes | Intersil Corporation | |
| Logotipo |  |
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HI5702
August 1997
10-Bit, 40 MSPS A/D Converter
Features
Description
• Sampling Rate . . . . . . . . . . . . . . . . . . . . . . . . . 40 MSPS
• 8.3 Bits Guaranteed at fIN = 10MHz
• Low Power
• Wide Full Power Input Bandwidth . . . . . . . . . . 250MHz
• Sample and Hold Not Required
• Single-Ended or Differential Input
• Input Signal Range . . . . . . . . . . . . . . . . . . . . . . . . 1.25V
• Single Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . +5V
• TTL Compatible Interface
Applications
• Professional Video Digitizing
• Medical Imaging
• Digital Communication Systems
• High Speed Data Acquisition
www.DataSheet4U.com
The HI5702 is a monolithic, 10-bit, analog-to-digital
converter fabricated in a BiCMOS process. It is designed for
high speed applications where wide bandwidth and low
power consumption are essential. Its 40 MSPS speed is
made possible by a fully differential pipeline architecture
which also eliminates the need for an external sample and
hold circuit. The HI5702 has excellent dynamic performance
while consuming <650mW power at 40 MSPS. Data output
latches are provided which present valid data to the output
bus with a latency of 7 clock cycles.
Refer to the HI5703, HI5746, or HI5767 data sheets for lower
power consumption.
Ordering Information
PART SAMPLE TEMP.
NUMBER RATE RANGE (oC) PACKAGE
PKG.
NO.
HI5702KCB 40 MSPS 0 to 70 28 Ld SOIC (W) M28.3
HI5702JCB 36 MSPS 0 to 70 28 Ld SOIC (W) M28.3
HI5702-EV2
25 Evaluation Board
Pinout
HI5702
(SOIC)
TOP VIEW
DVCC 1
DGND 2
DVCC 3
DGND 4
AVCC 5
AGND 6
VREF+ 7
VREF- 8
VIN+ 9
VIN- 10
VCM 11
AGND 12
AVCC 13
AGND 14
Typical Application Schematic
HI5702
28 D0
27 D1
26 D2
25 D3
24 D4
23 DVCC
22 CLK
21 DGND
20 D5
19 D6
18 D7
17 D8
16 D9
15 DFS
3.25V
2.0V
VIN +
VIN -
CLOCK
VREF+ (7)
VREF- (8)
(LSB) (28) D0
(27) D1
AGND (12)
AGND (6)
AGND (14)
DGND (2)
(26) D2
(25) D3
(24) D4
(20) D5
DGND (21) (19) D6
DGND (4) (18) D7
(17) D8
(MSB) (16) D9
VIN+ (9) (1) DVCC
VCM (11) (3) DVCC
VIN- (10) (23) DVCC
CLK (22) (13) AVCC
DFS (15) (5) AVCC
D0
D1
D2
D3 DGND
D4
D5
D6
D7
D8
D9
AGND
BNC
10µF AND 0.1µF CAPS
ARE PLACED AS CLOSE
TO PART AS POSSIBLE
+
0.1µF 10µF
+
0.1µF 10µF
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999
4-1505
File Number 3745.4
1 page  
Timing Waveforms
ANALOG
INPUT
HI5702
CLOCK
INPUT SN - 1 HN - 1 SN
HN SN + 1 HN + 1 SN + 2
SN + 5 HN + 5 SN + 6 HN + 6 SN + 7 HN + 7 SN + 8 HN + 8
INPUT
S/H
1ST
STAGE
2ND
STAGE
B1, N - 1
B1, N
B1, N + 1
B1, N + 4
B1, N + 5
B1, N + 6
B1, N + 7
B2, N - 2
B2, N - 1
B2, N
B2, N + 4
B2, N + 5
B2, N + 6
10TH
STAGE
B10, N - 5
B10, N - 4
B10, N
B10, N + 1
B10, N + 2
B10, N + 3
DATA
UTPUT
DN - 7
DN - 6
DN - 2
DN - 1
tLAT
NOTES:
1. SN: N-th sampling period.
2. HN: N-th holding period.
3. BM, N: M-th stage digital output corresponding to N-th sampled input.
4. DN: Final data output corresponding to N-th sampled input.
FIGURE 8. HI5702 INTERNAL CIRCUIT TIMING
DN
DN + 1
ANALOG
INPUT
CLOCK
INPUT
DATA
OUTPUT
1.5V
tAP
tAJ
1.5V
DATA N - 1
tOD
tH
2.0V
0.8V
DATA N
FIGURE 9. INPUT-TO-OUTPUT TIMING
4-1509
5 Page 
HI5702
Signal-to-Noise Ratio (SNR)
Full Power Input Bandwidth (FPBW)
SNR is the measured RMS signal to RMS noise at a speci-
fied input and sampling frequency. The noise is the RMS
sum of all of the spectral components except the fundamen-
tal and the first five harmonics.
Signal-to-Noise + Distortion Ratio (SINAD)
SINAD is the measured RMS signal to RMS sum of all
other spectral components below the Nyquist frequency
excluding DC.
Effective Number of Bits (ENOB)
The effective number of bits (ENOB) is calculated from the
SINAD data by
ENOB = (SINAD - 1.76 + VCORR) / 6.02
where: VCORR = 0.5dB
VCORR adjusts the ENOB for the amount the input is below
fullscale.
Total Harmonic Distortion (THD)
THD is the ratio of the RMS sum of the first 5 harmonic
components to the RMS value of the fundamental input signal.
2nd and 3rd Harmonic Distortion
This is the ratio of the RMS value of the applicable harmonic
component to the RMS value of the fundamental input signal.
Intermodulation Distortion (IMD)
Nonlinearities in the signal path will tend to generate
intermodulation products when two tones, f1 and f2, are
present on the inputs. The ratio of the measured signal to
the distortion terms is calculated. The terms included in the
calculation are (f1 + f2), (f1 - f2), (2f1), (2f2), (2f1 + f2),
(2f1 - f2), (f1 + 2f2), (f1 - 2f2). The ADC is tested with each
tone 6dB below full scale.
Spurious Free Dynamic Range (SFDR)
SFDR is the ratio of the fundamental RMS amplitude to the
RMS amplitude of the next largest spur or spectral compo-
nent in the spectrum below fS/2.
Transient Response
Transient response is measured by providing a full scale
transition to the analog input of the ADC and measuring the
number of cycles it takes for the output code to settle within
10-bit accuracy.
Overvoltage Recovery
Overvoltage Recovery is measured by providing a full scale
transition to the analog input of the ADC which overdrives
the input by 200mV, and measuring the number of cycles it
takes for the output code to settle within 10-bit accuracy.
Full power bandwidth is the frequency at which the ampli-
tude of the digitally reconstructed output has decreased 3dB
below the amplitude of the input sine wave. The input sine
wave has a peak-to-peak amplitude equal to the reference
voltage. The bandwidth given is measured at the specified
sampling frequency.
Video Definitions
Differential gain and Differential Phase are two commonly
found video specifications for characterizing the distortion of
a chrominance (3.58MHz) signal as it is offset through the
input voltage range of an ADC.
Differential Gain (DG)
Differential Gain is the peak difference in chrominance
amplitude (in percent) at two different DC levels.
Differential Phase (DP)
Differential Phase is the peak difference in chrominance
phase (in degrees) at two different DC levels.
Timing Definitions
Refer to Figure 1 and Figure 2 for these definitions.
Aperture Delay (tAD)
Aperture delay is the time delay between the external sam-
ple command (the falling edge of the clock) and the time at
which the signal is actually sampled. This delay is due to
internal clock path propagation delays.
Aperture Jitter (tAJ)
This is the RMS variation in the aperture delay due to varia-
tion of internal clock path delays.
Data Hold Time (tH)
Data hold time is the time to where the previous data (N - 1)
is no longer valid.
Data Output Delay Time (tOD)
Data output delay time is the time to where the new data (N)
is valid.
Data Latency (tLAT)
After the analog sample is taken, the data on the bus is out-
put at 7th cycle of the clock. This is due to the pipeline
nature of the converter where the data has to ripple through
the stages. This delay is specified as the data latency. After
the data latency time, the data representing each succeed-
ing sample is output at the following clock pulse. The digital
data lags the analog input by 7 cycles.
Power-Up Initialization
This time is defined as the maximum number of clock cycles
that are required to initialize the converter at power-up. The
requirement arises from the need to initialize the dynamic
circuits within the converter.
4-1515
11 Page | ||
| Páginas | Total 14 Páginas | |
| PDF Descargar | [ Datasheet HI5702.PDF ] | |
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