HI5905N PDF даташит
Спецификация HI5905N изготовлена «Intersil Corporation» и имеет функцию, называемую «A/D Converter». |
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Детали детали
Номер произв | HI5905N |
Описание | A/D Converter |
Производители | Intersil Corporation |
логотип |
8 Pages
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TM
Data Sheet
HI5905N/QML
July 1999 File Number 4718.1
14-Bit, 5 MSPS, Military A/D Converter
The HI5905N/QML is a monolithic, 14-bit, 5MSPS Analog-
to-Digital Converter fabricated in an advanced BiCMOS
process. It is designed for high speed, high resolution
applications where wide bandwidth, low power consumption
and excellent SINAD performance are essential. With a
100MHz full power input bandwidth and high frequency
accuracy, the converter is ideal for many Military types of
communication systems employing digital IF architectures.
The HI5905N/QML is designed in a fully differential pipelined
architecture with a front end differential-in-differential-out
sample-and-hold amplifier (S/H). Consuming 350mW (typ)
power at 5MSPS, the HI5905N/QML has excellent dynamic
performance over the full Military temperature range.
Data output latches are provided which present valid data to
the output bus with a data latency of only 4 clock cycles.
Specifications for QML devices are controlled by the
Defense Supply Center in Columbus (DSCC). The SMD
numbers listed below must be used when ordering.
Detailed Electrical Specifications for the HI5905N/QML
are contained in SMD 5962-98591. That document may
be easily downloaded from our website.
http://www.Intersil.com/data/sm/index.htm
Pinout
HI5905 (MQFP) (MO-108AA-2 ISSUE A)
TOP VIEW
NC
NC
DGND1
NC
AVCC
AGND
NC
NC
VIN+
VIN-
VDC
44 43 42 41 40 39 38 37 36 35 34
1 33
2 32
3 31
4 30
5 29
6 28
7 27
8 26
9 25
10 24
11 23
12 13 14 15 16 17 18 19 20 21 22
D3
D4
D5
D6
D7
NC
DVCC2
DGND2
D8
D9
NC
Features
• QML Compliant per SMD 5962-9859101NXB
• Sampling Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . .5MSPS
• Low Power at 5MSPS. . . . . . . . . . . . . . . . . 400mW (Max)
• Internal Sample and Hold
• Fully Differential Architecture
• Full Power Input Bandwidth . . . . . . . . . . . . . . . . . 100MHz
• SINAD at 1MHz . . . . . . . . . . . . . . . . . . . . . . >69dB (Min)
• Internal Voltage Reference
• TTL Compatible Clock Input
• CMOS Compatible Digital Data Outputs
Applications
• Digital Communication Systems
• Undersampling Digital IF
• Asymmetric Digital Subscriber Line (ADSL)
• Document Scanners
• Reference Literature
- AN9214, Using Intersil High Speed A/D Converters
- AN9785, Using the Intersil HI5905 EVAL2 Evaluation
Board
Ordering Information
ORDERING
NUMBER
INTERNAL INTERSIL
MKT. NUMBER
5962-9859101NXB HI5905N/QML
HI5905EVAL2
Low Frequency Platform
TEMP.
RANGE(oC)
-55 to 125
25
4-1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-724-7143 | Copyright © Intersil Corporation 1999
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Functional Block Diagram
VDC
VIN-
VIN+
S/H
BIAS
STAGE 1
+
∑-
X8
4-BIT
FLASH
4-BIT
DAC
STAGE 4
+
∑-
X8
4-BIT
FLASH
4-BIT
DAC
STAGE 5
4-BIT
FLASH
AVCC AGND DVCC1 DGND1
Typical Application Schematic
VIN+
VIN-
CLOCK
+5V +
10µF
0.1µF
(LSB) D0 (38)
VROUT (13)
VRIN (14)
AGND (6)
AGND (15)
DGND1 (3)
DGND1 (42)
DGND2 (26)
D1 (37)
D2 (36)
D3 (33)
D4 (32)
D5 (31)
D6 (30)
D7 (29)
D8 (25)
VIN+ (9)
VDC (11)
VIN- (10)
D9 (24)
D10 (21)
D11 (20)
D12 (19)
(MSB) D13 (18)
CLK (40)
DVCC1 (41)
AVCC (5) DVCC1 (43)
AVCC (16)DVCC2 (27)
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
0.1µF
HI5905
4-2
CLOCK
REF
CLK
VROUT
VRIN
DVCC2
D13 (MSB)
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0 (LSB)
DGND2
DGND
AGND
BNC
10µF AND 0.1µF CAPS ARE PLACED
AS CLOSE TO PART AS POSSIBLE
+5V
+10µF
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Timing Waveforms
ANALOG
INPUT
CLOCK
INPUT SN - 1 HN - 1 SN
HN SN + 1 HN + 1 SN + 2 HN + 2 SN + 3 HN + 3 SN + 4 HN + 4 SN + 5 HN + 5 SN + 6 HN + 6
INPUT
S/H
1ST
STAGE
B1, N - 1
B1, N
B1, N + 1
B1, N + 2
B1, N + 3
B1, N + 4
B1, N + 5
2ND
STAGE
3RD
STAGE
4TH
STAGE
B2, N - 2
B2, N - 1
B2, N
B2, N + 1
B2, N + 2
B2, N + 3
B2, N + 4
B3, N - 2
B3 , N - 1
B3, N
B3, N + 1
B3, N + 2
B3, N + 3
B3, N + 4
B4, N - 3
B4, N - 2
B4, N - 1
B4, N
B4, N + 1
B4, N + 2
B4, N + 3
5TH
STAGE
DATA
OUTPUT
B5, N - 3
DN - 4
NOTES:
1. SN: N-th sampling period.
2. HN: N-th holding period.
B5, N - 2
B5, N - 1
B5, N
B5, N + 1
B5, N + 2
B5, N + 3
DN - 3
DN - 2
DN - 1
DN
DN + 1
DN + 2
tLAT
3. BM, N: M-th stage digital output corresponding to N-th sampled input.
4. DN: Final data output corresponding to N-th sampled input.
FIGURE 1. INTERNAL CIRCUIT TIMING
ANALOG
INPUT
tAP
tAJ
CLOCK
INPUT
1.5V
1.5V
tOD
tH
DATA
OUTPUT
DATA N-1
3.5V
1.5V
DATA N
FIGURE 2. INPUT-TO-OUTPUT TIMING
4-3
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