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HI5634 PDF даташит

Спецификация HI5634 изготовлена ​​​​«Intersil Corporation» и имеет функцию, называемую «High Performance Programmable Phase-Locked Loop».

Детали детали

Номер произв HI5634
Описание High Performance Programmable Phase-Locked Loop
Производители Intersil Corporation
логотип Intersil Corporation логотип 

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HI5634 Даташит, Описание, Даташиты
PRELIMINARY
Data Sheet
HI5634
May 1999
File Number 4745
High Performance Programmable
Phase-Locked Loop for LCD Applications
The HI5634 is a low cost but very high-performance
frequency generator for line-locked and genlocked high
resolution video applications. Utilizing an advanced low
voltage CMOS mixed signal technology, the HI5634 is an
effective clock solution for video projectors and displays at
resolutions from VGA to beyond UXGA
The HI5634 offers pixel clock outputs in both differential (to
250MHz) and single-ended (to 150MHz) formats. Digital
phase adjustment circuitry allows user control of the pixel
clock phase relative to the recovered sync signal. A second
differential output at half the pixel clock rate enables
deMUXing of multiplexed A/D converters. The FUNC pin
provides either the regenerated input from the phase-locked
loop (PLL) divider chain output or a re-synchronized and
sharpened input HSYNC.
The advanced PLL utilizes either its internal programmable
feedback divider or an external divider. The device is
programmed by a standard I2C-bus® serial interface.
Simplified Block Diagram
www.DataSheet4U.com
LOOP FILTER
OSC
HSYNC
I2C INTERFACE
PHASE
LOCKED
LOOP
DIGITAL
PHASE
ADJUST
CLK
CLK/2
FUNC
Ordering Information
TEMP.
PART NUMBER RANGE (oC)
PACKAGE
HI5634CB
0 to 70 24 Ld SOIC
PKG.
NO.
M24.3
Features
• Pixel Clock Frequencies up to 250MHz
• Very Low Jitter
• Digital Phase Adjustment (DPA) for Clock Outputs
• Balanced PECL Differential Outputs
• Single-Ended SSTL_3 Clock Outputs
• Double-Buffered PLL/DPA Control Registers
• Independent Software Reset for PLL/DPA
• External or Internal Loop Filter Selection
• Uses 3.3V Supply. Inputs are 5V Tolerant.
• I2C-bus Serial Interface can Run at Either Low Speed
(100kHz) or High Speed (400kHz)
• Lock Detection
Applications
• LCD Monitors and Video Projectors
• Genlocking Multiple Video Subsystems
• Frequency Synthesis
Pinout
HI5634
(SOIC)
TOP VIEW
VDDD 1
VSSD 2
SDA 3
SCL 4
PDEN 5
EXTFB 6
HSYNC 7
EXTFIL 8
EXTFILRET 9
VDDA 10
VSSA 11
OSC 12
24 IREF
23 CLK/2+ (PECL)
22 CLK/2- (PECL)
21 CLK+ (PECL)
20 CLK- (PECL)
19 VSSQ
18 VDDQ
17 CLK (SSTL)
16 CLK/2 (SSTL)
15 FUNC (SSTL)
14 LOCK/REF (SSTL)
13 I2CADR
1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999
I2C Bus is a Trademark of Philips Corporation.









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HI5634 Даташит, Описание, Даташиты
HI5634
Pin Descriptions
PIN NO.
PIN NAME
1 VDDD
2 VSSD
3 SDA
4 SCL
5 PDEN
6 EXTFB
7 HSYNC
8 EXTFIL
9 EXTFILRET
10 VDDA
11 VSSA
12 OSC
13 I2CADR
14 LOCK/REF (SSTL)
15 FUNC (SSTL)
16 CLK/2 (SSTL)
17 CLK (SSTL)
18 VDDQ
19 VSSQ
20 CLK- (PECL)
21 CLK+ (PECL)
22 CLK/2- (PECL)
23 CLK/2+ (PECL)
24 IREF
NOTES:
1. These LVTTL inputs are 5V tolerant.
2. Connect to ground if unused.
TYPE
PWR
PWR
IN/OUT
IN
IN
IN
IN
IN
IN
PWR
PWR
IN
IN
OUT
OUT
OUT
OUT
PWR
PWR
OUT
OUT
OUT
OUT
IN
DESCRIPTION
Digital Supply
Digital Ground
Serial Data
Serial Clock
PFD Enable
External Feedback In
Horizontal Sync
External Filter
External Filter Return
Analog Supply
Analog Ground
Oscillator
I2C Address
Lock Indicator/Reference
Function Output
Pixel Clock/2 Out
Pixel Clock Out
Output Driver Supply
Output Driver Ground
Pixel Clock Out
Pixel Clock Out
Pixel Clock/2 Out
Pixel Clock/2 Out
Reference Current
COMMENTS
3.3V to Digital Sections
I2C-Bus (Note 1)
I2C-Bus (Note 1)
Suspends Charge Pump (Note1)
External Divider Input to PFD (Note1)
Clock Input to PLL (Note1)
External PLL Loop Filter
External PLL Loop Filter Return
3.3V for Analog Circuitry
Ground for Analog Circuitry
Input From Crystal Oscillator Package (Notes 1, 2)
Chip I2C Address Select
Low = 4Dh Read, 4Ch Write
High = 4Fh Read, 4Eh Write
Displays PLL or DPA Lock or REF Input
SSTL_3 Selectable HSYNC Output
SSTL_3 Driver to ADC DeMUX Input
SSTL_3 Driver to ADC
3.3V to Output Drivers
Ground for Output Drivers
Inverted PECL Driver to ADC. Open Drain Output.
PECL Driver to ADC. Open Drain Output.
Inverted PECL Driver to ADC DeMUX Input. Open Drain
Output.
PECL Driver to ADC DeMUX Input. Open Drain Output.
Reference Current for PECL Outputs
2









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HI5634 Даташит, Описание, Даташиты
Block Diagram
HI5634
3










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HI5634High Performance Programmable Phase-Locked LoopIntersil Corporation
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