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PDF W3E232M16S-XSTX Data sheet ( Hoja de datos )
| Número de pieza | W3E232M16S-XSTX | |
| Descripción | 2x32Mx16bit DDR SDRAM | |
| Fabricantes | White Electronic | |
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White Electronic Designs
W3E232M16S-XSTX
PRELIMINARY*
www.DataSheet4U.com
2x32Mx16bit DDR SDRAM
FEATURES
Double-data-rate architecture; two data transfers
per clock cycle
Data rate = 200, 266, 333, 400 Mbs
Package:
• 66pin TSOP II package
2.5V ±0.2V core power supply
2.5V I/O (SSTL_2 compatible)
Differential clock inputs(CK and CK#)
DLL aligns DQ and DQS transition with CK
MRS cycle with address key programs
• Read latency : 2, 2.5 , 3 (Clock)
• Burst length (2, 4, or 8)
• Burst type (sequential & interleave)
Auto & Self refresh Modes
RoHS Compliant
Commands entered on each positive CK edge
Internal pipelined double-data-rate (DDR)
architecture; two data accesses per clock cycle
Bidirectional data strobe (DQS) transmitted/
received with data, i.e., source-synchronous data
capture (one per byte)
DQS edge-aligned with data for READs; center-
aligned with data for WRITEs
Four internal banks for concurrent operation
Data mask (DM) pins for masking write data
(one per byte)
Programmable IOL/IOH option
Auto precharge option
Auto Refresh and Self Refresh Modes
Commercial, and Industrial Temperature Ranges
Organized as 2X32M x 16
* This product is under development, is not qualified +and is subject to change
without notice.
Speed @CL2
Speed @CL2.5
Speed @CL3
* CL = CAS Latency
DDR400
—
166MHz
200MHz
OPERATING FREQUENCIES
DDR333
133MHz
166MHz
—
DDR266
133MHz
133MHz
—
FUNCTIONAL BLOCK DIAGRAM
CK, CK#, CAS, LDM, UDM
RAS#, WE#, UDQS, LDQS
CS0#, CKE0
32Mx16
CS1#, CKE1
32Mx16
A0-A12, BA0, BA1
I/O0 ~ I/O15
DDR200
100MHz
133MHz
—
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
December 2005
Rev. 1
1 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
1 page  
White Electronic Designs
W3E232M16S-XSTX
PRELIMINARY*
be brought HIGH. Following the NOP command, a
PRECHARGE ALL command should be applied. Next a
LOAD MODE REGISTER command should be issued for
the extended mode register (BA1 LOW and BA0 HIGH)
to enable the DLL, followed by another LOAD MODE
REGISTER command to the mode register (BA0/BA1
both LOW) to reset the DLL and to program the operating
parameters. Two-hundred clock cycles are required
between the DLL reset and any READ command. A
PRECHARGE ALL command should then be applied,
placing the device in the all banks idle state.
Once in the idle state, two AUTO REFRESH cycles must
be performed (tRFC must be satisfied.) Additionally, a LOAD
MODE REGISTER command for the mode register with
the reset DLL bit deactivated (i.e., to program operating
parameters without resetting the DLL) is required.
Following these requirements, the DDR SDRAM is ready
for normal operation.
REGISTER DEFINITION
MODE REGISTER
The Mode Register is used to define the specific mode of
operation of the DDR SDRAM. This definition includes the
selection of a burst length, a burst type, a CAS latency,
and an operating mode, as shown in Figure 3. The Mode
Register is programmed via the MODE REGISTER SET
command (with BA0 = 0 and BA1 = 0) and will retain
the stored information until it is programmed again or
the device loses power. (Except for bit A8 which is self
clearing).
Reprogramming the mode register will not alter the contents
of the memory, provided it is performed correctly. The Mode
Register must be loaded (reloaded) when all banks are
idle and no bursts are in progress, and the controller must
wait the specified time before initiating the subsequent
operation. Violating either of these requirements will result
in unspecified operation.
Mode register bits A0-A2 specify the burst length, A3
specifies the type of burst (sequential or interleaved),
A4-A6 specify the CAS latency, and A7-A12 specify the
operating mode.
BURST LENGTH
Read and write accesses to the DDR SDRAM are burst
oriented, with the burst length being programmable,
as shown in Figure 3. The burst length determines
the maximum number of column locations that can be
accessed for a given READ or WRITE command. Burst
lengths of 2, 4 or 8 locations are available for both the
sequential and the interleaved burst types.
Reserved states should not be used, as unknown operation
or incompatibility with future versions may result.
When a READ or WRITE command is issued, a block of
columns equal to the burst length is effectively selected.
All accesses for that burst take place within this block,
meaning that the burst will wrap within the block if a
boundary is reached. The block is uniquely selected by
A1-Ai when the burst length is set to two; by A2-Ai when the
burst length is set to four (where Ai is the most significant
column address for a given configuration); and by A3-Ai
when the burst length is set to eight. The remaining (least
significant) address bit(s) is (are) used to select the starting
location within the block. The programmed burst length
applies to both READ and WRITE bursts.
BURST TYPE
Accesses within a given burst may be programmed to be
either sequential or interleaved; this is referred to as the
burst type and is selected via bit M3.
The ordering of accesses within a burst is determined by
the burst length, the burst type and the starting column
address, as shown in Table 1.
READ LATENCY
The READ latency is the delay, in clock cycles, between
the registration of a READ command and the availability
of the first bit of output data. The latency can be set to 2
or 2.5 clocks.
If a READ command is registered at clock edge n, and the
latency is m clocks, the data will be available by clock edge
n+m. Table 2 below indicates the operating frequencies at
which each CAS latency setting can be used.
Reserved states should not be used as unknown operation
or incompatibility with future versions may result.
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
December 2005
Rev. 1
5 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
5 Page 
White Electronic Designs
W3E232M16S-XSTX
PRELIMINARY*
ABSOLUTE MAXIMUM RATINGS
Parameter
Voltage on VCC, VCCQ Supply relative to Vss
Voltage on I/O pins relative to Vss
Operating Temperature TA (Mil)
Operating Temperature TA (Ind)
Storage Temperature, Plastic
-1 to 3.6
-0.5V to VCCQ +0.5V
-55 to +125
-40 to +85
-55 to +125
Unit
V
V
°C
°C
°C
NOTE:Stress greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the
device at these or any other conditions greater than those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect reliability.
Parameter
Input Capacitance: CK/CK#
Addresses, BA0-1 Input Capacitance
Input Capacitance: All other input-only pins
Input/Output Capacitance: I/Os
CAPACITANCE (NOTE 13)
Symbol
CI1
CA
CI2
CIO
Max
6
8
6
10
Unit
pF
pF
pF
pF
DC ELECTRICAL CHARACTERISTICS AND OPERATING CONDITIONS (NOTES 1-5, 16)
VCC, VCCQ = +2.5V ± 0.2V; -55°C ≤ TA ≤ +125°C
Parameter/Condition
Supply Voltage (36, 41)
I/O Supply Voltage (36, 41, 44)
Supply Voltage 400Mbs (36,40)
I/O Supply Voltage 400Mbs (36, 41, 44)
Input Leakage Current: Any input 0V ≤ VIN ≤ VCC (All other pins not under test = 0V)
Output Leakage Current: I/Os are disabled; 0V ≤ VOUT ≤ VCCQ
Output Levels: Full drive option (37, 39)
High Current (VOUT = VCCQ - 0.373V, minimum VREF, minimum VTT)
Low Current (VOUT = 0.373V, maximum VREF, maximum VTT)
Output Levels: Reduced drive option (38, 39)
High Current (VOUT = VCCQ - 0.763V, minimum VREF, minimum VTT)
Low Current (VOUT = 0.763V, maximum VREF, maximum VTT)
I/O Reference Voltage (6,44)
I/O Termination Voltage (7, 44)
Symbol
VCC
VCCQ
VCC
VCCQ
II
IOZ
IOH
IOL
IOHR
IOLR
VREF
VTT
Min
2.3
2.3
2.5
2.5
-4
-10
-12
12
-9
9
0.49 x VCCQ
VREF - 0.04
Max
2.7
2.7
2.7
2.7
4
10
-
-
-
-
0.51 x VCCQ
VREF + 0.04
Units
V
V
V
V
µA
µA
mA
mA
mA
mA
V
V
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
December 2005
Rev. 1
11 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
11 Page | ||
| Páginas | Total 22 Páginas | |
| PDF Descargar | [ Datasheet W3E232M16S-XSTX.PDF ] | |
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