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W3E32M72S-XSBX PDF даташит

Спецификация W3E32M72S-XSBX изготовлена ​​​​«White Electronic» и имеет функцию, называемую «32Mx72 DDR SDRAM».

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Номер произв W3E32M72S-XSBX
Описание 32Mx72 DDR SDRAM
Производители White Electronic
логотип White Electronic логотип 

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W3E32M72S-XSBX Даташит, Описание, Даташиты
White Electronic Designs
W3E32M72S-XSBX
32Mx72 DDR SDRAM
FEATURES
„ Data rate = 200, 250, 266, 333Mbs
„ Package:
• 208 Plastic Ball Grid Array (PBGA), 16 x 22mm
„ 2.5V ±0.2V core power supply
„ 2.5V I/O (SSTL_2 compatible)
„ Differential clock inputs (CK and CK#)
„ Commands entered on each positive CK edge
„ Internal pipelined double-data-rate (DDR)
architecture; two data accesses per clock cycle
„ Programmable Burst length: 2,4 or 8
„ Bidirectional data strobe (DQS) transmitted/
received with data, i.e., source-synchronous data
capture (one per byte)
„ DQS edge-aligned with data for READs; center-
aligned with data for WRITEs
„ DLLwww.DataSheet4U.com to align DQ and DQS transitions with CK
„ Four internal banks for concurrent operation
„ Data mask (DM) pins for masking write data
(one per byte)
„ Programmable IOL/IOH option
„ Auto precharge option
„ Auto Refresh and Self Refresh Modes
„ Commercial, Industrial and Military
TemperatureRanges
„ Organized as 32M x 72
„ Weight: W3E32M72S-XSBX - 2.5 grams typical
* This product is subject to change without notice.
BENEFITS
„ 73% Space Savings vs. TSOP
• 44% Space Savings vs FPBGA
„ Reduced part count
„ 37% I/O reduction vs TSOP
• 31% I/O reduction vs FPBGA
„ Reduced trace lengths for lower parasitic
capacitance
„ Suitable for hi-reliability applications
„ Laminate interposer for optimum TCE match
„ Upgradeable to 64M x 72 density (contact factory
for information)
GENERAL DESCRIPTION
The 256MByte (2Gb) DDR SDRAM is a high-speed CMOS,
dynamic random-access, memory using 5 chips containing
536,870,912 bits. Each chip is internally configured as a
quad-bank DRAM.
The 256MB DDR SDRAM uses a double data rate
architecture to achieve high-speed operation. The
double data rate architecture is essentially a 2n-prefetch
architecture with an interface designed to transfer two data
words per clock cycle at the I/O pins. A single read or write
access for the 256MB DDR SDRAM effectively consists
of a single 2n-bit wide, one-clock-cycle data tansfer at the
internal DRAM core and two corresponding n-bit wide,
one-half-clock-cycle data transfers at the I/O pins.
A bi-directional data strobe (DQS) is transmitted
externally, along with data, for use in data capture at the
receiver.strobe transmitted by the DDR SDRAM during
READs and by the memory contoller during WRITEs. DQS
is edge-aligned with data for READs and center-aligned
with data for WRITEs. Each chip has two data strobes, one
for the lower byte and one for the upper byte.
The 256MB DDR SDRAM operates from a differential clock
(CK and CK#); the crossing of CK going HIGH and CK#
going LOW will be referred to as the positive edge of CK.
Commands (address and control signals) are registered
at every positive edge of CK. Input data is registered on
both edges of DQS, and output data is referenced to both
edges of DQS, as well as to both edges of CK.
White Electronic Designs Corp. reserves the right to change products or specications without notice.
July 2006
Rev. 6
1 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com









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W3E32M72S-XSBX Даташит, Описание, Даташиты
White Electronic Designs
W3E32M72S-XSBX
DENSITY COMPARISONS
11.9
TSOP Approach (mm)
11.9 11.9 11.9
11.9
22.3
66
TSOP
66
TSOP
66
TSOP
66
TSOP
66
TSOP
Area
I/O
Count
5 x 265mm2 = 1325mm2
5 x 66 pins = 330 pins
10.0
12.5
60
FBGA
CSP Approach (mm)
10.0 10.0 10.0
60
FBGA
60
FBGA
60
FBGA
10.0
60
FBGA
Area
I/O
Count
5 x 125mm2 = 625mm2
5 x 60 balls = 300 balls
Actual Size
W3E32M72S-XSBX
22
16
S
A
V
I
N
G
S
352mm2
73%
208 Balls
37%
Actual Size
W3E32M72S-XSBX
22
16
352mm2
S
A
V
I
N
G
S
44%
208 Balls
31%
Read and write accesses to the DDR SDRAM are burst
oriented; accesses start at a selected location and continue
for a programmed number of locations in a programmed
sequence. Accesses begin with the registration of an
ACTIVE command, which is then followed by a READ or
WRITE command. The address bits registered coincident
with the ACTIVE command are used to select the bank
and row to be accessed. The address bits registered
coincident with the READ or WRITE command are used
to select the bank and the starting column location for the
burst access.
The DDR SDRAM provides for programmable READ
or WRITE burst lengths of 2, 4, or 8 locations. An auto
precharge function may be enabled to provide a self-
timed row precharge that is initiated at the end of the
burst access.
The pipelined, multibank architecture of DDR SDRAMs allows
for concurrent operation, thereby providing high effective
bandwidth by hiding row precharge and activation time.
An auto refresh mode is provided, along with a power-
saving power-down mode. All inputs are compatible with
the Jedec Standard for SSTL_2. All full drive options
outputs are SSTL_2, Class II compatible.
FUNCTIONAL DESCRIPTION
Read and write accesses to the DDR SDRAM are burst
oriented; accesses start at a selected location and continue
for a programmed number of locations in a programmed
sequence. Accesses begin with the registration of an
ACTIVE command which is then followed by a READ or
WRITE command. The address bits registered coincident
with the ACTIVE command are used to select the bank and
row to be accessed (BA0 and BA1 select the bank, A0-12
select the row). The address bits registered coincident
with the READ or WRITE command are used to select the
starting column location for the burst access.
Prior to normal operation, the DDR SDRAM must be
initialized. The following sections provide detailed
information covering device initialization, register denition,
command descriptions and device operation.
White Electronic Designs Corp. reserves the right to change products or specications without notice.
July 2006
Rev. 6
2 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com









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W3E32M72S-XSBX Даташит, Описание, Даташиты
White Electronic Designs
W3E32M72S-XSBX
FIG. 1 PIN CONFIGURATION
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
TOP VIEW
1 2 3 4 5 6 7 8 9 10 11
VCC VSS VCCQ VCCQ VSS VCCQ VCCQ VSS VCC VSS
VCCQ
VSS
CS2
CS0
CKE2
CKE0
CAS2
RAS0
RAS2
VSS
VCCQ
VSS CK0 CK2 CK0 CK2 DQML0 DQML2 CAS0 WE0 WE2 VSS
DQMH2 DQMH0 DQSH2 DQSH0 DQ8 DQ40 DQ5 DQ39 DQ7 DQSL2 DQSL0
DQ41
DQ9
DQ10
DQ42
DQ43
DQ12
DQ3
DQ36
DQ4
DQ38
DQ6
DQ44 DQ11
DQ13
DQ45
DQ14
DQ33
DQ1
DQ34
DQ2
DQ37
DQ35
DQ64
DQ65
DQ15
DQ47
DQ46
VSS
DQ32
DQ0
DQ77
DQ79
DQ78
DNU
DQ66
DQ69
DNU
DQ67
VCC
DQ72
DQ73
DQ74
DQ75
DQ76
VCCQ
A12
BA1
A0
VCC VSS VCCQ A7
A9
DNU*
VCC
VSS A10
A3 VCCQ VSS VREF VSS VCCQ A4
A11 VSS
VCC A2
BA0
A1
VCCQ
VSS
VCC
A6
A8
A5 VCCQ
DQ71 DQ70 DQSL4 DQML4 DQ68
VCC DQSH4 DQMH4 CK4#
CK4
DNU
WE4# CAS4# RAS4# DQ16 DQ48
VSS
DQ63
DQ31
DQ62
CKE4
CS4#
DQ22
DQ52
DQ18
DQ50
DQ17
DQ49
DQ30
DQ61
DQ29 DQ59
DQ27
DQ23
DQ54
DQ21
DQ19
DQ51
DQ60
DQ28
DQ58
DQ26 DQ57
DQ25
DQSL1 DQSL3 DQ55
DQ53
DQ20
DQ56
DQ24 DQMH3 DQMH1 DQSH1 DQSH3
VSS CAS3 WE3# WE1# DQML3 DQML1 CK1 CK3 CK1 CK3 VSS
VCCQ
VSS
CAS1# RAS3# RAS1# CKE1
CKE3
CS1
CS3
VSS VCCQ
VSS VCC VSS VCCQ VCCQ VSS VCCQ VCCQ VSS VCC VSS
* pin J10 is reserved for signal A13 on future upgrades.
NOTE: DNU = Do Not Use.
White Electronic Designs Corp. reserves the right to change products or specications without notice.
July 2006
Rev. 6
3 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com










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