PDF W3EG64255S-JD3 Data sheet ( Hoja de datos )

Número de pieza	W3EG64255S-JD3
Descripción	2GB - 2x128Mx64 DDR SDRAM REGISTERED
Fabricantes	White Electronic
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No Preview Available ! White Electronic Designs W3EG64255S-JD3 ADVANCED* 2GB – 2x128Mx64 DDR SDRAM REGISTERED, w/PLL FEATURES Double-data-rate architecture DDR200, DDR266 and DDR333; • JEDEC design speciﬁcations Bi-directional data strobes (DQS) Differential clock inputs (CK & CK#) Programmable Read Latency 2,2.5 (clock) Programmable Burst Length (2,4,8) Programmable Burst type (sequential & interleave) Edge aligned data output, center aligned data input. Auto and self refresh Serial presence detect Dual Rank Power supply: VCC 2.5V ± 0.2V www.DataSheet4U.com JEDEC standard 184 pin DIMM package • JD3: 30.48 (1.20") DESCRIPTION The W3EG64255S is a 2x128Mx64 Double Data Rate SDRAM memory module based on 512Mb DDR SDRAM component. The module consists of sixteen 256Mx4 stacks, in 66 pin TSOP packages mounted on a 184 pin FR4 substrate. Synchronous design allows precise cycle control with the use of system clock. Data I/O transactions are possible on both edges and Burst Lengths allow the same device to be useful for a variety of high bandwidth, high performance memory system applications. * This product is under development, is not qualiﬁed or characterized and is subject to change or cancellation without notice. NOTE: Consult factory for availability of: • RoHS compliant products • Vendor source control options • Industrial temperature option Clock Speed CL-tRCD-tRP DDR333 @CL=2.5 166MHz 2.5-3-3 OPERATING FREQUENCIES DDR266 @CL=2 133MHz 2-2-2 DDR266 @CL=2 133MHz 2-3-3 DDR266 @CL=2.5 133MHz 2.5-3-3 DDR200 @CL=2 100MHz 2-2-2 April 2005 Rev. 3 1 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com 1 page White Electronic Designs W3EG64255S-JD3 ADVANCED Parameter Operating Current Operating Current Precharge Power- Down Standby Current Idle Standby Current Active Power-Down Standby Current Active Standby Current Operating Current Operating Current Auto Refresh Current Self Refresh Current Operating Current IDD SPECIFICATIONS AND TEST CONDITIONS 0°C ≤ TA ≤ +70°C, VCCQ = 2.5V ± 0.2V, VCC = 2.5V ± 0.2V. Includes DDR SDRAM components only Rank 1 Symbol Conditions IDD0 One device bank; Active - Precharge; tRC = tRC (MIN); tCK = tCK (MIN); DQ,DM and DQS inputs changing once per clock cycle; Address and control inputs changing once every two cycles. IDD1 One device bank; Active-Read- Precharge Burst = 2; tRC = tRC (MIN); tCK = tCK (MIN); lOUT = 0mA; Address and control inputs changing once per clock cycle. IDD2P All device banks idle; Power-down mode; tCK = tCK (MIN); CKE = (low) IDD2F CS# = High; All device banks idle; tCK = tCK (MIN); CKE = High; Address and other control inputs changing once per clock cycle. VIN = VREF for DQ, DQS and DM. IDD3P One device bank active; Power-Down mode; tCK (MIN); CKE = (low) IDD3N CS# = High; CKE = High; One device bank; Active-Precharge;tRC = tRAS (MAX); tCK = tCK (MIN); DQ, DM and DQS inputs changing twice per clock cycle; Address and other control inputs changing once per clock cycle. IDD4R Burst = 2; Reads; Continuous burst; One device bank active; Address and control inputs changing once per clock cycle; tCK = tCK (MIN); lOUT = 0mA. IDD4W Burst = 2; Writes; Continuous burst; One device bank active; Address and control inputs changing once per clock cycle; tCK = tCK (MIN); DQ,DM and DQS inputs changing once per clock cycle. IDD5 tRC = tRC (MIN) IDD6 CKE ≤ 0.2V IDD7A Four bank interleaving Reads (BL=4) with auto precharge with tRC=tRC (MIN); tCK=tCK(MIN); Address and control inputs change only during Active Read or Write commands. DDR333@CL=2.5 Max 4140 4680 180 1620 1260 1800 4770 4590 7020 180 9090 DDR266:@CL=2, 2.5 Max 4140 4680 180 1620 1260 1800 4770 4590 7020 180 9000 DDR200@CL=2 Max 3690 4230 180 1440 1080 1620 4230 4050 6660 180 7920 Units mA Rank 2 Standby State IDD3N mA IDD3N rnA IDD2P mA IDD2F mA IDD3P mA IDD3N mA IDD3N rnA IDD3N mA IDD3N mA IDD6 mA IDD3N April 2005 Rev. 3 5 White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com 5 Page White Electronic Designs PART NUMBERING GUIDE W3EG64255S-JD3 ADVANCED WEDC SDRAM DDR GOLD BUS WIDTH DEPTH (Dual Rank): 255 = 256Mb 2.5V SPEED (MHz): 166, 133, 100MHZ PACKAGE: JD3 COMPONENT VENDOR: (M = Micron, S = Samsung, G = Inﬁneon) G = RoHS COMPLIANT W 3 E G 64 255M S xxx JD3 x G April 2005 Rev. 3 11 White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com 11 Page

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