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PDF W3EG6462S-D3 Data sheet ( Hoja de datos )
| Número de pieza | W3EG6462S-D3 | |
| Descripción | 512MB - 2x32Mx64 DDR SDRAM UNBUFFERED | |
| Fabricantes | White Electronic | |
| Logotipo |  |
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White Electronic Designs
W3EG6462S-D3
-JD3
ADVANCED*
512MB – 2x32Mx64 DDR SDRAM UNBUFFERED
FEATURES
Double-data-rate architecture
DDR200, DDR266, DDR333 and DDR400
• JEDEC design specified
Bi-directional data strobes (DQS)
Differential clock inputs (CK & CK#)
Programmable Read Latency 2,2.5 (clock)
Programmable Burst Length (2,4,8)
Programmable Burst type (sequential & interleave)
Edge aligned data output, center aligned data input.
Auto and self refresh
Serial presence detect
Dual Rank
Power supply:
• VCC = VCCQ = +2.5V ±0.2V (100, 133 and 166
MHz)www.DataSheet4U.com
• VCC = VCCQ = +2.6V ±0.1V (200 MHz)
Standard 184 pin DIMM package
• JD3 PCB height: 30.48 (1.20") MAX
DESCRIPTION
The W3EG6462S is a 2x32Mx64 Double Data Rate
SDRAM memory module based on 256Mb DDR SDRAM
components. The module consists of sixteen 32Mx8 DDR
SDRAMs in 66 pin TSOP packages mounted on a 184 pin
FR4 substrate.
Synchronous design allows precise cycle control with the
use of system clock. Data I/O transactions are possible on
both edges and Burst Lengths allow the same device to be
useful for a variety of high bandwidth, high performance
memory system applications.
* This product is under development, is not qualified or characterized and is subject to
change or cancellation without notice.
NOTE: Consult factory for availability of:
• RoHS compliant products
• Vendor source control options
• Industrial temperature option
Clock Speed
CL-tRCD-tRP
DDR400 @CL=3
200MHz
3-3-3
OPERATING FREQUENCIES
DDR333 @CL=2.5 DDR266 @CL=2.5 DDR266 @CL=2
166MHz
133MHz
133MHz
2.5-3-3
2-3-3
2-3-3
DDR266 @CL=2.5
133MHz
2.5-3-3
DDR200 @CL=2
100MHz
2-2-2
May 2005
Rev. 4
1 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
1 page  
White Electronic Designs
W3EG6462S-D3
-JD3
ADVANCED
IDD SPECIFICATIONS AND TEST CONDITIONS
0°C ≤ TA ≤ 70°C, VCCQ = 2.5V ± 0.2V, VCC = 2.5V ± 0.2V
Includes DDR SDRAM component only
Parameter
Operating Current
Operating Current
Precharge Power-
Down Standby
Current
Idle Standby Current
Active Power-Down
Standby Current
Active Standby
Current
Operating Current
Operating Current
Auto Refresh Current
Self Refresh Current
Operating Current
Symbol
IDD0
IDD1
IDD2P
Conditions
One device bank; Active - Precharge;
tRC=tRC (MIN); tCK=tCK (MIN); DQ,DM
and DQS inputs changing once per
clock cycle; Address and control inputs
changing once every two cycles.
One device bank; Active-Read-
Precharge Burst = 2; tRC=tRC (MIN);
tCK=tCK (MIN); lOUT = 0mA; Address
and control inputs changing once per
clock cycle.
All device banks idle; Power-down
mode; tCK=tCK (MIN); CKE=(low)
DDR400@
CL=3
Max
2200
2480
64
DDR333@
CL=2.5-3-3
Max
1960
2320
64
DDR266@
CL=2
Max
1800
2080
64
IDD2F CS# = High; All device banks idle;
960 800 720
tCK=tCK (MIN); CKE = high; Address
and other control inputs changing once
per clock cycle. VIN = VREF for DQ,
DQS and DM.
IDD3P One device bank active; Power-Down
640
480
400
mode; tCK (MIN); CKE=(low)
IDD3N CS# = High; CKE = High; One device
1120
960
800
bank; Active-Precharge; tRC=tRAS
(MAX); tCK=tCK (MIN); DQ, DM and
DQS inputs changing twice per clock
cycle; Address and other control inputs
changing once per clock cycle.
IDD4R Burst = 2; Reads; Continuous burst; 2720 2360 2000
One device bank active; Address and
control inputs changing once per clock
cycle; TCK= TCK (MIN); lOUT = 0mA.
IDD4W Burst = 2; Writes; Continuous burst; 2680 2360 2000
One device bank active; Address and
control inputs changing once per clock
cycle; tCK=tCK (MIN); DQ,DM and DQS
inputs changing once per clock cycle.
IDD5 tRC = tRC (MIN)
3200 3000 2680
IDD6 CKE ≤ 0.2V
64 64 64
IDD7A Four bank interleaving Reads (BL=4)
4880
4240
3600
with auto precharge with tRC=tRC (MIN);
tCK=tCK (MIN); Address and control
inputs change only during Active Read
or Write commands.
DDR266@
CL=2.5
Max
1800
2080
64
720
400
800
2000
2000
2680
64
3600
DDR200@
CL=2
Max
1800
2080
64
720
400
800
2000
2000
2680
64
3600
Units
mA
mA
rnA
mA
mA
mA
mA
rnA
mA
mA
mA
May 2005
Rev. 4
5 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
5 Page 
White Electronic Designs
W3EG6462S-D3
-JD3
ADVANCED
ORDERING INFORMATION FOR JD3
Part Number
W3EG6462S403JD3
Speed
200MHz/400Mb/s
CAS Latency
3
tRCD
3
tRP Height*
3 30.48 (1.20")
W3EG6462S335JD3
166MHz/333Mb/s
2.5 3 3 30.48 (1.20")
W3EG6462S262JD3
133MHz/266Mb/s
2 2 2 30.48 (1.20")
W3EG6462S263JD3
133MHz/266Mb/s
2 3 3 30.48 (1.20")
W3EG6462S265JD3
133MHz/266Mb/s
2.5 3 3 30.48 (1.20")
W3EG6462S202JD3
100MHz/200Mb/s
2 2 2 30.48 (1.20")
NOTES:
• Consult Factory for availability of RoHS compliant products. (G = RoHS Compliant)
• Vendor specific part numbers are used to provide memory components source control. The place holder for this is shown as lower case “x” in the part numbers above and is to
be replaced with the respective vendors code. Consult factory for qualified sourcing options. (M = Micron, S = Samsung & consult factory for others)
• Consult factory for availability of industrial temperature (-40°C to 85°C) option
PACKAGE DIMENSIONS FOR JD3
3.99
(0.157 (2x))
17.78
(0.700)
10.01
(0.394)
6.35
(0.250)
133.48
(5.255" MAX.)
131.34
(5.171")
128.95
(5.077")
64.77
(2.550)
6.35
(0.250)
1.78
(0.070)
1.27
49.53 (0.050 TYP.)
(1.950)
3.81
(0.150 MAX)
30.48
(1.20)
MAX
3.99
(0.157)
(MIN)
2.31
(0.091)
(2x)
3.00
(0.118)
(4x)
1.27 ± 0.10
(0.050 ± 0.004)
* ALL DIMENSIONS ARE IN MILLIMETERS AND (INCHES)
May 2005
Rev. 4
11 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
11 Page | ||
| Páginas | Total 13 Páginas | |
| PDF Descargar | [ Datasheet W3EG6462S-D3.PDF ] | |
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