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PDF W3EG6464S-JD3 Data sheet ( Hoja de datos )
| Número de pieza | W3EG6464S-JD3 | |
| Descripción | 512MB - 64Mx64 DDR SDRAM UNBUFFERED | |
| Fabricantes | White Electronic | |
| Logotipo |  |
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White Electronic Designs
W3EG6464S-JD3-D3
PRELIMINARY*
512MB – 64Mx64 DDR SDRAM UNBUFFERED
FEATURES
Double-data-rate architecture
DDR200 and DDR266
• JEDEC design specification
Bi-directional data strobes (DQS)
Differential clock inputs (CK & CK#)
Programmable Read Latency 2,2.5 (clock)
Programmable Burst Length (2,4,8)
Programmable Burst type (sequential & interleave)
Edge aligned data output, center aligned data input.
Auto and self refresh
Serial presence detect
Power supply: VCC: 2.5V ± 0.20V
JEDEC standard 184 pin DIMM package
• Package height option:
www.DataSheet4U.com
JD3: 30.48mm (1.20")
DESCRIPTION
The W3EG6464S is a 64Mx64 Double Data Rate
SDRAM memory module based on 512Mb DDR SDRAM
components. The module consists of eight 64Mx8 DDR
SDRAMs in 66 pin TSOP packages mounted on a 184
pin FR4 substrate.
Synchronous design allows precise cycle control with the
use of system clock. Data I/O transactions are possible on
both edges and Burst Lengths allow the same device to be
useful for a variety of high bandwidth, high performance
memory system applications.
* This product is under development, is not qualified or characterized and is subject to
change without notice.
NOTE: Consult factory for availability of:
• Lead-Free Products
• Vendor source control options
• Industrial temperature options
Clock Speed
CL-tRCD-tRP
OPERATING FREQUENCIES
DDR266 @CL=2
133MHz
2-2-2
DDR266 @CL=2.5
133MHz
2.5-3-3
DDR266 @CL=2
133MHz
2-3-3
DDR200 @CL=2
100MHz
2-2-2
May 2005
Rev. 3
1 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
1 page  
White Electronic Designs
W3EG6464S-JD3-D3
PRELIMINARY
IDD SPECIFICATIONS AND TEST CONDITIONS
0°C ≤ TA ≤ 70°C, VCCQ = 2.5V ± 0.2V, VCC = 2.5V ± 0.2V
Includes DDR SDRAM component only
Parameter
Operating Current
Symbol
IDD0
Operating Current
IDD1
Precharge Power-
Down Standby
Current
Idle Standby Current
IDD2P
IDD2F
Active Power-Down
Standby Current
Active Standby
Current
IDD3P
IDD3N
Operating Current
IDD4R
Operating Current
IDD4W
Auto Refresh Current
Self Refresh Current
IDD5
IDD6
Operating Current
IDD7A
Conditions
One device bank; Active - Precharge; tRC=tRC
(MIN); tCK=tCK (MIN); DQ,DM and DQS inputs
changing once per clock cycle; Address and control
inputs changing once every two cycles.
One device bank; Active-Read-Precharge Burst
= 2; tRC=tRC (MIN); tCK=tCK (MIN); lOUT = 0mA;
Address and control inputs changing once per
clock cycle.
All device banks idle; Power-down mode; tCK=tCK
(MIN); CKE=(low)
CS# = High; All device banks idle; tCK=tCK (MIN);
CKE = high; Address and other control inputs
changing once per clock cycle. VIN = VREF for DQ,
DQS and DM.
One device bank active; Power-Down mode; tCK
(MIN); CKE=(low)
CS# = High; CKE = High; One device bank; Active-
Precharge; tRC=tRAS (MAX); tCK=tCK (MIN); DQ, DM
and DQS inputs changing twice per clock cycle;
Address and other control inputs changing once
per clock cycle.
Burst = 2; Reads; Continuous burst; One device
bank active; Address and control inputs changing
once per clock cycle; TCK= TCK (MIN); lOUT = 0mA.
Burst = 2; Writes; Continuous burst; One device
bank active; Address and control inputs changing
once per clock cycle; tCK=tCK (MIN); DQ,DM and
DQS inputs changing once per clock cycle.
tRC = tRC (MIN)
CKE ≤ 0.2V
Standard
Low Power
Four bank interleaving Reads (BL=4) with auto
precharge with tRC=tRC (MIN); tCK=tCK (MIN);
Address and control inputs change only during
Active Read or Write commands.
DDR266@CL=2
Max
1320
1520
48
400
400
760
1760
2000
2480
40
25
3840
DDR266@CL=2.5
Max
1320
1520
48
400
400
760
1760
2000
2480
40
25
3840
DDR266 &
200@CL=2
Max
1320
1520
48
400
400
760
1760
2000
2480
40
25
3840
Units
mA
mA
rnA
mA
mA
mA
mA
rnA
mA
mA
mA
May 2005
Rev. 3
5 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
5 Page 
White Electronic Designs
W3EG6464S-JD3-D3
PRELIMINARY
ORDERING INFORMATION FOR D3
Part Number
Speed
CAS Latency tRCD
tRP
Height*
W3EG6464S262D3
133MHz/266Mb/s
2
2 2 30.48 (1.20")
W3EG6464S263D3
133MHz/266Mb/s
2
3 3 30.48 (1.20")
W3EG6464S265D3
133MHz/266Mb/s
2.5
3 3 30.48 (1.20")
W3EG6464S202D3
100MHz/200Mb/s
2
2 2 30.48 (1.20")
NOTES:
• Consult Factory for availability of Lead-Free products. (F = Lead-Free, G = RoHS Compliant)
• Product specific part numbers are available for source control if needed, please consult factory for the correct part number if a specific component vendor is preferred.
• Consult factory for availability of industrial temperature (-40°C to 85°C) option
PACKAGE DIMENSIONS FOR D3
133.48
(5.255" MAX.)
131.34
ended3.99
(0.157 (2x))
Not RecomDemsigns.17.78
(0.700)
For New10.01
(0.394)
(5.171")
128.95
(5.077")
64.77
6.35
(0.250)
1.27
49.53 (0.050 TYP.)
(1.950)
6.35
(0.250)
(2.550)
1.78
(0.070)
30.48
(1.20)
MAX
2.31
(0.091)
(2x)
3.00
(0.118)
(4x)
2.54
(0.100)
MAX
3.99
(0.157)
(MIN)
1.27 ± 0.10
(0.050 ± 0.004)
* ALL DIMENSIONS ARE IN MILLIMETERS AND (INCHES)
May 2005
Rev. 3
11 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
11 Page | ||
| Páginas | Total 12 Páginas | |
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