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PDF W3EG72126S-JD3 Data sheet ( Hoja de datos )
| Número de pieza | W3EG72126S-JD3 | |
| Descripción | 1GB-128Mx72 DDR SDRAM REGISTERED ECC | |
| Fabricantes | White Electronic | |
| Logotipo |  |
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White Electronic Designs
W3EG72126S-D3
-JD3
-AJD3
PRELIMINARY*
1GB-128Mx72 DDR SDRAM REGISTERED ECC w/PLL
FEATURES
Double-data-rate architecture
DDR200, DDR266 and DDR333:
• JEDEC design specifications
Bi-directional data strobes (DQS)
Differential clock inputs (CK & CK#)
Programmable Read Latency 2,2.5 (clock)
Programmable Burst Length (2,4,8)
Programmable Burst type (sequential & interleave)
Edge aligned data output, center aligned data input.
Auto and self refresh
Serial presence detect
Power supply: VCC = 2.5V ± 0.20V
JEDEC standard 184 pin DIMM package
• Package height options:
www.DataSheet4U.com JD3: 30.48mm (1.20") and
AJD3: 28.70mm (1.13")
• Consult factory for availability of lead-free
products.
DESCRIPTION
The W3EG72126S is a 128Mx72 Double Data Rate
SDRAM memory module based on 512Mb DDR SDRAM
components. The module consists of eighteen 128Mx4
DDR SDRAMs in 66 pin TSOP packages mounted on a
184 pin FR4 substrate.
Synchronous design allows precise cycle control with the
use of system clock. Data I/O transactions are possible on
both edges and Burst Lengths allow the same device to be
useful for a variety of high bandwidth, high performance
memory system applications.
* This product is under development, is not qualified or characterized and is subject to
change without notice.
Clock Speed
CL-tRCD-tRP
DDR333 @CL=2.5
166MHz
2.5-3-3
OPERATING FREQUENCIES
DDR266 @CL=2
133MHz
2-2-2
DDR266 @CL=2
133MHz
2-3-3
DDR266 @CL=2.5
133MHz
2.5-3-3
DDR200 @CL=2
100MHz
2-2-2
November 2004
Rev. 3
1 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
1 page  
White Electronic Designs
W3EG72126S-D3
-JD3
-AJD3
PRELIMINARY
IDD SPECIFICATIONS AND TEST CONDITIONS
0°C ≤ TA ≤ 70°C, VCCQ = 2.5V ± 0.2V, VCC = 2.5V ± 0.2V
Includes DDR SDRAM component only
Parameter
Symbol Conditions
Operating Current
IDD0 One device bank; Active - Precharge;
tRC=tRC (MIN); tCK=tCK (MIN); DQ,DM
and DQS inputs changing once per
clock cycle; Address and control
inputs changing once every two
cycles.
Operating Current
IDD1 One device bank; Active-Read-
Precharge Burst = 2; tRC=tRC (MIN);
tCK=tCK (MIN); lOUT = 0mA; Address
and control inputs changing once per
clock cycle.
Precharge Power-
Down Standby
Current
IDD2P All device banks idle; Power-down
mode; tCK=tCK (MIN); CKE=(low)
Idle Standby Current IDD2F CS# = High; All device banks idle;
tCK=tCK (MIN); CKE = high; Address
and other control inputs changing
once per clock cycle. VIN = VREF for
DQ, DQS and DM.
Active Power-Down
Standby Current
IDD3P One device bank active; Power-Down
mode; tCK (MIN); CKE=(low)
Active Standby
Current
IDD3N CS# = High; CKE = High; One device
bank; Active-Precharge; tRC=tRAS
(MAX); tCK=tCK (MIN); DQ, DM and
DQS inputs changing twice per clock
cycle; Address and other control
inputs changing once per clock cycle.
Operating Current
IDD4R Burst = 2; Reads; Continuous burst;
One device bank active; Address
and control inputs changing once
per clock cycle; TCK= TCK (MIN); lOUT
= 0mA.
Operating Current
IDD4W Burst = 2; Writes; Continuous burst;
One device bank active; Address
and control inputs changing once per
clock cycle; tCK=tCK (MIN); DQ,DM
and DQS inputs changing once per
clock cycle.
Auto Refresh
Current
IDD5 tRC = tRC (MIN)
Self Refresh Current IDD6 CKE ≤ 0.2V
Operating Current
IDD7A Four bank interleaving Reads (BL=4)
with auto precharge with tRC=tRC
(MIN); tCK=tCK (MIN); Address and
control inputs change only during
Active Read or Write commands.
DDR333@CL=2.5
Max
2340
2880
90
810
630
900
2970
3150
5220
90
7290
DDR266@CL=2, 2.5
Max
2340
2880
90
810
630
900
2970
2790
5220
90
7200
DDR200@CL=2
Max
2340
2880
90
810
630
900
2970
2790
5220
90
7200
Units
mA
mA
rnA
mA
mA
mA
mA
rnA
mA
mA
mA
November 2004
Rev. 3
5 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
5 Page 
White Electronic Designs
W3EG72126S-D3
-JD3
-AJD3
PRELIMINARY
ORDERING INFORMATION FOR JD3
Part Number
Speed
CAS Latency tRCD
W3EG72126S335JD3
166MHz/333Mb/s
2.5
3
W3EG72126S262JD3
133MHz/266Mb/s
2
2
W3EG72126S263JD3
133MHz/266Mb/s
2
3
W3EG72126S265JD3
133MHz/266Mb/s
2.5
3
W3EG72126S202JD3
100MHz/200Mb/s
2
2
Note: Consult factory for availability of lead-free products. (F = Lead-Free, G = RoHS compliant)
Vendor Code: M = Micron, S = Samsung
tRP
3
2
3
3
2
Height*
30.48 (1.20")
30.48 (1.20")
30.48 (1.20")
30.48 (1.20")
30.48 (1.20")
PACKAGE DIMENSIONS FOR JD3
3.99
(0.157 (2x))
17.78
(0.700)
10.01
(0.394)
6.35
(0.250)
133.48
(5.255" MAX.)
131.34
(5.171")
128.95
(5.077")
64.77
(2.550)
6.35
(0.250)
1.78
(0.070)
3.81
(0.150 MAX)
1.27
49.53 (0.050 TYP.)
(1.950)
3.99
30.48
(0.157)
(1.20 MAX) (MIN)
2.31
(0.091)
(2x)
3.00
(0.118)
(4x)
1.27 ± 0.10
(0.050 ± 0.004)
November 2004
Rev. 3
* ALL DIMENSIONS ARE IN MILLIMETERS AND (INCHES)
11 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
11 Page | ||
| Páginas | Total 15 Páginas | |
| PDF Descargar | [ Datasheet W3EG72126S-JD3.PDF ] | |
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