PDF W3EG7232S-AD4 Data sheet ( Hoja de datos )

Número de pieza	W3EG7232S-AD4
Descripción	256MB - 32Mx72 DDR SDRAM UNBUFFERED
Fabricantes	White Electronic
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No Preview Available ! White Electronic Designs W3EG7232S-AD4 -BD4 PRELIMINARY* 256MB – 32Mx72 DDR SDRAM UNBUFFERED w/PLL FEATURES Double-data-rate architecture DDR200, DDR266 and DDR300 • JEDEC design speciﬁcations Bi-directional data strobes (DQS) Differential clock inputs (CK & CK#) Programmable Read Latency 2,2.5 (clock) Programmable Burst Length (2,4,8) Programmable Burst type (sequential & interleave) Edge aligned data output, center aligned data input Auto and self refresh Serial presence detect Power supply: 2.5V ± 0.2V JEDEC standard 200 pin SO-DIMM package • Package height options: www.DataSheet4U.com AD4: 35.5 mm (1.38") and BD4: 31.75 mm (1.25") DESCRIPTION The W3EG7232S is a 32Mx72 Double Data Rate SDRAM memory module based on 256Mb DDR SDRAM components. The module consists of nine 32Mx8 DDR SDRAMs in 66 pin TSOP packages mounted on a 200 pin FR4 substrate. Synchronous design allows precise cycle control with the use of system clock. Data I/O transactions are possible on both edges and Burst Lengths allow the same device to be useful for a variety of high bandwidth, high performance memory system applications. * This product is under development, is not qualiﬁed or characterized and is subject to change without notice. NOTE: Consult factory for availability of: • RoHS compliant products • Vendor source control options • Industrial temperature option Clock Speed CL-tRCD-tRP OPERATING FREQUENCIES DDR333 @CL=2.5 166MHz 2.5-3-3 DDR266 @CL=2 133MHz 2-2-2 DDR266 @CL=2.5 133MHz 2.5-3-3 DDR200 @CL=2 100MHz 2-2-2 August 2005 Rev. 4 1 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com 1 page White Electronic Designs W3EG7232S-AD4 -BD4 PRELIMINARY IDD SPECIFICATIONS AND TEST CONDITIONS 0°C ≤ TA ≤ 70°C, VCCQ = 2.5V ± 0.2V, VCC = 2.5V ± 0.2V DDR333@ DDR266@ CL=2.5 CL=2, 2.5 Parameter Symbol Conditions Operating Current IDD0 One device bank; Active - Precharge; (MIN); DQ,DM and DQS inputs changing once per clock cycle; Address and control inputs changing once every two cycles. TRC=TRC(MIN); TCK=TCK Operating Current IDD1 One device bank; Active-Read-Precharge; Burst = 2; TRC=TRC(MIN);TCK=TCK (MIN); Iout = 0mA; Address and control inputs changing once per clock cycle. Precharge Power-Down IDD2P All device banks idle; Power-down mode; TCK=TCK(MIN); Standby Current CKE=(low) Max 1400 1805 36 Max 1400 1805 36 Idle Standby Current Active Power-Down Standby Current Active Standby Current Operating Current Operating Current IDD2F IDD3P IDD3N IDD4R IDD4W CS# = High; All device banks idle; TCK=TCK(MIN); CKE = high; Address and other control inputs changing once per clock cycle. VIN = VREF for DQ, DQS and DM. One device bank active; Power-down mode; TCK(MIN); CKE=(low) CS# = High; CKE = High; One device bank; Active-Precharge; TRC=TRAS(MAX); TCK=TCK(MIN); DQ, DM and DQS inputs changing twice per clock cycle; Address and other control inputs changing once per clock cycle. Burst = 2; Reads; Continous burst; One device bank active;Address andcontrol inputs changing once per clock cycle; TCK=TCK(MIN); IOUT = 0mA. Burst = 2; Writes; Continous burst; One device bank active; Address and control inputs changing once per clock cycle; TCK=TCK(MIN); DQ,DM and DQS inputs changing twice per clock cycle. 725 270 815 1850 1850 725 270 815 1850 1850 Auto Refresh Current Self Refresh Current Operating Current IDD5 TRC=TRC(MIN) IDD6 CKE ≤ 0.2V IDD7A Four bank interleaving Reads (BL=4) with auto precharge with TRC=TRC (MIN); TCK=TCK(MIN); Address and control inputs change only during Active Read or Write commands 2570 311 3965 2570 311 3965 DDR200@ CL=2 Max 1400 1715 36 680 225 725 1625 1625 2390 311 3425 Units mA mA mA mA mA mA mA mA mA mA mA August 2005 Rev. 4 5 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com 5 Page White Electronic Designs W3EG7232S-AD4 -BD4 PRELIMINARY ORDERING INFORMATION FOR BD4 Part Number Speed Height* W3EG7232S335BD4-x 166MHz/333Mbps, CL=2.5 31.75 (1.25") W3EG7232S262BD4-x 133MHz/266Mbps, CL=2 31.75 (1.25") W3EG7232S265BD4-x 133MHz/266Mbps, CL=2.5 31.75 (1.25") W3EG7232S202BD4-x 100MHz/200Mbps, CL=2 31.75 (1.25") NOTES: • Consult Factory for availability of RoHS compliant products. (G = RoHS Compliant) • Vendor speciﬁc part numbers are used to provide memory components source control. The place holder for this is shown as lower case “x” in the part numbers above and is to be replaced with the respective vendors code. Consult factory for qualiﬁed sourcing options. (M = Micron, S = Samsung & consult factory for others) • Consult factory for availability of industrial temperature (-40°C to 85°C) option PACKAGE DIMENSIONS FOR BD4 3.98 ± 0.1 (0.157 ± 0.004) 67.56 (2.666) MAX 2.31 (0.091) REF. 11.40 (0.449) 4.19 (0.165) 1.80 (0.071) 47.40 (1.866) 3.81 (0.150) MAX. 31.75 (1.25) 20 (0.787) 3.98 (0.157) MIN. 1.0 ± 0.1 (0.039 ± 0.004) * ALL DIMENSIONS ARE IN MILLIMETERS AND (INCHES) August 2005 Rev. 4 11 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com 11 Page

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