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PDF W3EG7234S-D3 Data sheet ( Hoja de datos )
| Número de pieza | W3EG7234S-D3 | |
| Descripción | 256MB - 32Mx72 DDR SDRAM REGISTERED | |
| Fabricantes | White Electronic | |
| Logotipo |  |
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White Electronic Designs
W3EG7234S-D3
-JD3
-AJD3
PRELIMINARY*
256MB - 32Mx72 DDR SDRAM REGISTERED, w/PLL
FEATURES
Double-data-rate architecture
Clock speeds: 100MHz and 133MHz
Bi-directional data strobes (DQS)
Differential clock inputs (CK & CK#)
Programmable Read Latency 2,2,5 (clock)
Programmable Burst Length (2,4,8)
Programmable Burst type (sequential & interleave)
Edge aligned data output, center aligned data input
Auto and self refresh
Serial presence detect
Power Supply: 2.5V ± 0.20V
JEDEC standard 184 pin DIMM package
•
www.DataSheet4U.com
Package height options:
JD3: 30.48mm (1.20")
AJD3: 28.70mm (1.13")
DESCRIPTION
The W3EG7234S is a 32Mx72 Double Data Rate
SDRAM memory module based on 128Mb DDR
SDRAM component. The module consists of eighteen
32Mx4 DDR SDRAMs in 66 pin TSOP package
mounted on a 184 Pin FR4 substrate.
Synchronous design allows precise cycle control with
the use of system clock. Data I/O transactions are
possible on both edges and Burst Lenths allow the
same device to be useful for a variety of high bandwidth,
high performance memory system applications.
* This product is under development, is not qualified or characterized and is subject to
change without notice.
Clock Speed
CL-tRCD-tRP
OPERATING FREQUENCIES
DDR266 @CL=2
133MHz
2-2-2
DDR266 @CL=2.5
133MHz
2.5-3-3
DDR200 @CL=2
100MHz
2-2-2
December 2004
Rev. 2
1 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
1 page  
White Electronic Designs
W3EG7234S-D3
-JD3
-AJD3
PRELIMINARY
Parameter
Operating Current
Operating Current
Precharge Power-
Down Standby Current
Idle Standby Current
Active Power-Down
Standby Current
Active Standby Current
Operating Current
Operating Current
Auto Refresh Current
Self Refresh Current
Operating Current
IDD SPECIFICATIONS AND TEST CONDITIONS
0°C ≤ TA ≤ 70°C, VCCQ = 2.5V ± 0.2V, VCC = 2.5V ± 0.2V
Includes PLL and Register Power
Symbol
IDD0
IDD1
IDD2P
IDD2F
IDD3P
IDD3N
IDD4R
IDD4W
IDD5
IDD6
IDD7A
Rank 1
Conditions
One device bank; Active - Precharge; tRC
= tRC (MIN); tCK = tCK (MIN); DQ,DM and
DQS inputs changing once per clock cycle;
Address and control inputs changing once
every two cycles.
One device bank; Active-Read-Precharge
Burst = 2; tRC = tRC (MIN); tCK = tCK (MIN);
lOUT = 0mA; Address and control inputs
changing once per clock cycle.
All device banks idle; Power-down mode;
tCK = tCK (MIN); CKE = (low)
CS# = High; All device banks idle;
tCK = tCK (MIN); CKE = High; Address
and other control inputs changing once
per clock cycle. VIN = VREF for DQ, DQS
and DM.
One device bank active; Power-Down
mode; tCK (MIN); CKE = (low)
CS# = High; CKE = High; One device
bank; Active-Precharge;tRC = tRAS (MAX);
tCK = tCK (MIN); DQ, DM and DQS inputs
changing twice per clock cycle; Address
and other control inputs changing once per
clock cycle.
Burst = 2; Reads; Continuous burst; One
device bank active; Address and control
inputs changing once per clock cycle; tCK =
tCK (MIN); lOUT = 0mA.
Burst = 2; Writes; Continuous burst; One
device bank active; Address and control
inputs changing once per clock cycle;
tCK = tCK (MIN); DQ,DM and DQS inputs
changing once per clock cycle.
tRC = tRC (MIN)
CKE ≤ 0.2V
Four bank interleaving Reads (BL=4)
with auto precharge with tRC=tRC (MIN);
tCK=tCK(MIN); Address and control inputs
change only during Active Read or Write
commands.
DDR266@CL=2
Max
2520
2700
54
1120
450
1210
2745
2700
3770
329
4860
DDR266@CL=2.5
Max
2385
2520
54
1030
360
1120
2610
2565
3680
311
4770
DDR200@CL=2
Max
2385
2520
54
1030
360
1120
2610
2565
3645
346
4770
Units
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
December 2004
Rev. 2
5 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
5 Page 
White Electronic Designs
Part Number
W3EG7234S262JD3
W3EG7234S265JD3
W3EG7234S202JD3
ORDERING INFORMATION FOR JD3
Speed
CAS Latency tRCD
133MHz/266Mb/s
2
2
133MHz/266Mb/s
2.5
3
100MHz/200Mb/s
2
2
W3EG7234S-D3
-JD3
-AJD3
PRELIMINARY
tRP Height*
2 30.48 (1.20")
3 30.48 (1.20")
2 30.48 (1.20")
PACKAGE DIMENSIONS FOR JD3
3.99
(0.157 (2x))
17.78
(0.700)
10.01
(0.394)
6.35
(0.250)
133.48
(5.255" MAX.)
131.34
(5.171")
128.95
(5.077")
64.77
(2.550)
6.35
(0.250)
1.78
(0.070)
4.06
(0.160 MAX)
1.27
49.53 (0.050 TYP.)
(1.950)
3.99
30.48
(0.157)
(1.20 MAX) (MIN)
2.31
(0.091)
(2x)
3.00
(0.118)
(4x)
1.27 ± 0.10
(0.050 ± 0.004)
* ALL DIMENSIONS ARE IN MILLIMETERS AND (INCHES).
December 2004
Rev. 2
11 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
11 Page | ||
| Páginas | Total 14 Páginas | |
| PDF Descargar | [ Datasheet W3EG7234S-D3.PDF ] | |
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