PDF W3EG7235S-JD3 Data sheet ( Hoja de datos )

Número de pieza	W3EG7235S-JD3
Descripción	256MB - 2x16Mx72 DDR SDRAM REGISTERED ECC
Fabricantes	White Electronic
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No Preview Available ! White Electronic Designs W3EG7235S-JD3 PRELIMINARY* 256MB – 2x16Mx72 DDR SDRAM REGISTERED ECC, w/PLL FEATURES Double-data-rate architecture Speeds of 100MHz and 133MHz Bi-directional data strobes (DQS) Differential clock inputs (CK# & CK) Programmable Read Latency 2,2.5 (clock) Programmable Burst Length (2,4,8) Programmable Burst type (sequential & interleave) Edge aligned data output, center aligned data input Auto and self refresh Serial presence detect Dual Rank Power supply: 2.5V ± 0.20V JEDEC standard 184 pin DIMM package www.DataSheet4U.com • Package height option: JD3 30.48 mm (1:20") DESCRIPTION The WED3DG7235S is a 2x16Mx72 Double Data Rate SDRAM memory module based on 128Mb DDR SDRAM component. The module consists of eighteen 16Mx8 DDR SDRAMs in 66 pin TSOP packages mounted on a 184 pin FR4 substrate. Synchronous design allows precise cycle control with the use of system clock. Data I/O transactions are possible on both edges and Burst Lengths allow the same device to be useful for a variety of high bandwidth, high performance memory system applications. * This product is under development, is not qualiﬁed or characterized and is subject to change without notice. NOTE: Consult factory for availability of: • RoHS compliant products • Vendor source control options • Industrial temperature option Clock Speed CL-tRCD-tRP OPERATING FREQUENCIES DDR266 @CL=2 133MHz 2-2-2 DDR266 @CL=2.5 133MHz 2.5-3-3 DDR200 @CL=2 100MHz 2-2-2 November 2004 Rev. 2 1 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com 1 page White Electronic Designs W3EG7235S-JD3 PRELIMINARY Parameter Operating Current Operating Current Precharge Power- Down Standby Current dle Standby Current Active Power-Down Standby Current Active Standby Current Operating Current Operating Current Auto Refresh Current Self Refresh Current Operating Current Rank 1 IDD0 IDD1 IDD2P IDD2F IDD3P IDD3N IDD4R IDD4W IDD5 IDD6 IDD7A IDD SPECIFICATIONS AND TEST CONDITIONS 0°C ≤ TA ≤ 70°C, VCCQ = 2.5V ± 0.2V, VCC = 2.5V ± 0.2V Includes PLL and Register Power Conditions One device bank; Active = Precharge; tRC = tRC(MIN); tCK = tCK(MIN); DQ,DM and DQS inputs changing once per clock cycle; Address and control inputs changing once every two cycles. One device bank; Active-Read-Precharge; Burst = 2; tRC = tRC(MIN);tCK = tCK (MIN); Iout = 0mA; Address and control inputs changing once per clock cycle. All device banks idle; Power- down mode; tCK = tCK(MIN); CKE = (low) CS# = High; All device banks idle; tCK = tCK(MIN); CKE = high; Address and other control inputs changing once per clock cycle. VIN = VREF for DQ, DQS and DM. One device bank active; Power-down mode; tCK(MIN); CKE = (low) CS# = High; CKE = High; One device bank; Active- Precharge; tRC = tRAS(MAX); tCK = tCK(MIN); DQ, DM and DQS inputs changing twice per clock cycle; Address and other control inputs changing once per clock cycle. Burst = 2; Reads; Continuous burst; One device bank active; Address and control inputs changing once per clock cycle; tCK = tCK(MIN); IOUT = 0mA. Burst = 2; Writes; Continous burst; One device bank active; Address and control inputs changing once per clock cycle; tCK = tCK(MIN); DQ,DM and DQS inputs changing twice per clock cycle. tRC = tRC(MIN) CKE ≤ 0.2V Four bank interleaving Reads (BL = 4) with auto precharge with tRC = tRC (MIN); tCK = tCK(MIN); Address and control inputs change only during Active Read or Write commands. DDR266@CL = 2 Max 2475 2565 54 1120 450 1210 2655 2610 3500 329 4455 DDR266@CL = 2.5 Max 2340 2475 54 1030 360 1120 2520 2475 3410 311 4320 DDR200@CL = 2 Max 2340 2475 54 1030 360 1120 2520 2475 3375 346 4320 Rank2 Stand By Units State mA IDD3N mA IDD3N mA IDD2P mA IDD2F mA IDD3P mA IDD3N mA IDD3N mA IDD3N mA IDD3N mA IDD6 mA IDD3N November 2004 Rev. 2 5 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com 5 Page White Electronic Designs W3EG7235S-JD3 PRELIMINARY ORDER INFORMATION FOR JD3 Part Number W3EG7235S262JD3 W3EG7235S265JD3 W3EG7235S202JD3 Speed 133MHz/266Mbps 133MHz/266Mbps 100MHz/200Mbps CAS Latency 2 2.5 2 tRCD 2 3 2 tRP Height* 2 30.48 (1.20") 3 30.48 (1.20") 2 30.48 (1.20") NOTES: • Consult Factory for availability of RoHS compliant products. (G = RoHS Compliant) • Vendor speciﬁc part numbers are used to provide memory components source control. The place holder for this is shown as lower case “x” in the part numbers above and is to be replaced with the respective vendors code. Consult factory for qualiﬁed sourcing options. (M = Micron, S = Samsung & consult factory for others) • Consult factory for availability of industrial temperature (-40°C to 85°C) option PACKAGE DIMENSIONS FOR JD3 3.99 (0.157 (2x)) 17.78 (0.700) 10.01 (0.394) 6.35 (0.250) 133.48 (5.255" MAX.) 131.34 (5.171") 128.95 (5.077") 64.77 (2.550) 6.35 (0.250) 1.78 (0.070) 4.06 (0.160 MAX) 1.27 49.53 (0.050 TYP.) (1.950) 3.99 30.48 (0.157) (1.20 MAX) (MIN) 2.31 (0.091) (2x) 3.00 (0.118) (4x) 1.27 ± 0.10 (0.050 ± 0.004) ALL DIMENSIONS ARE IN MILLIMETERS AND (INCHES) November 2004 Rev. 2 11 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com 11 Page

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