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PDF W3EG7266S-D3 Data sheet ( Hoja de datos )
| Número de pieza | W3EG7266S-D3 | |
| Descripción | 512MB - 64Mx72 DDR SDRAM REGISTERED | |
| Fabricantes | White Electronic | |
| Logotipo |  |
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White Electronic Designs
W3EG7266S-D3
PRELIMINARY*
512MB – 64Mx72 DDR SDRAM REGISTERED w/PLL
FEATURES
Double-data-rate architecture
Clock speeds of 100MHz and 133MHz
Bi-directional data strobes (DQS)
Differential clock inputs (CK & CK#)
Programmable Read Latency 2,2,5 (clock)
Programmable Burst Length (2,4,8)
Programmable Burst type (sequential & interleave)
Edge aligned data output, center aligned data input
Auto and self refresh
Serial presence detect
Power Supply: 2.5V ± 0.20V
Standard 184 pin DIMM package
• D3 = 26.67mm (1.05")
www.DataSheet4U.com
DESCRIPTION
The W3EG7266S is a 64Mx72 Double Data Rate
SDRAM memory module based on 512Mb DDR SDRAM
component. The module consists of nine 64Mx8 DDR
SDRAMs in 66 pin TSOP package mounted on a 184 Pin
FR4 substrate.
Synchronous design allows precise cycle control with the
use of system clock. Data I/O transactions are possible on
both edges and Burst Lenths allow the same device to be
useful for a variety of high bandwidth, high performance
memory system applications.
* This product is under development, is not qualified or characterized and is subject to
change without notice.
NOTE: Consult factory for availability of:
• RoHS compliant products
• Vendor source control options
• Industrial temperature option
Clock Speed
CL-tRCD-tRP
OPERATING FREQUENCIES
DDR266 @CL=2
133MHz
2-2-2
DDR266 @CL=2.5
133MHz
2.5-3-3
DDR200 @CL=2
100MHz
2-2-2
October 2005
Rev. 3
1 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
1 page  
White Electronic Designs
W3EG7266S-D3
PRELIMINARY
IDD SPECIFICATIONS AND TEST CONDITIONS
Recommended operating conditions, 0°C ≤ TA ≤ 70°C, VCC = 2.5V ± 0.2V, VCC = 2.5V ± 0.2V
Includes DDR SDRAM component only
Parameter
Symbol Conditions
Operating Current
IDD0 One device bank; Active - Precharge;
tRC=tRC (MIN); tCK=tCK (MIN); DQ,DM
and DQS inputs changing once per
clock cycle; Address and control
inputs changing once every two
cycles.
Operating Current
IDD1 One device bank; Active-Read-
Precharge Burst = 2; tRC=tRC (MIN);
tCK=tCK (MIN); lOUT = 0mA; Address
and control inputs changing once per
clock cycle.
Precharge Power-
Down Standby
Current
IDD2P All device banks idle; Power-down
mode; tCK=tCK (MIN); CKE=(low)
Idle Standby Current IDD2F CS# = High; All device banks idle;
tCK=tCK (MIN); CKE = high; Address
and other control inputs changing
once per clock cycle. VIN = VREF for
DQ, DQS and DM.
Active Power-Down
Standby Current
IDD3P One device bank active; Power-Down
mode; tCK (MIN); CKE=(low)
Active Standby
Current
IDD3N CS# = High; CKE = High; One device
bank; Active-Precharge; tRC=tRAS
(MAX); tCK=tCK (MIN); DQ, DM and
DQS inputs changing twice per clock
cycle; Address and other control
inputs changing once per clock cycle.
Operating Current
IDD4R Burst = 2; Reads; Continuous burst;
One device bank active; Address
and control inputs changing once
per clock cycle; TCK= TCK (MIN); lOUT
= 0mA.
Operating Current
IDD4W Burst = 2; Writes; Continuous burst;
One device bank active; Address
and control inputs changing once per
clock cycle; tCK=tCK (MIN); DQ,DM
and DQS inputs changing once per
clock cycle.
Auto Refresh
Current
IDD5 tRC = tRC (MIN)
Self Refresh Current IDD6 CKE ≤ 0.2V
Operating Current
IDD7A Four bank interleaving Reads (BL=4)
with auto precharge with tRC=tRC
(MIN); tCK=tCK (MIN); Address and
control inputs change only during
Active Read or Write commands.
DDR266@CL=2
Max
1170
1440
45
405
315
450
1485
1440
2610
45
3600
DDR266@CL=2.5
Max
1170
1440
45
405
315
450
1485
1440
2610
45
3600
DDR200@CL=2
Max
1035
1305
45
360
270
450
1305
1215
2520
45
3150
Units
mA
mA
rnA
mA
mA
mA
mA
rnA
mA
mA
mA
October 2005
Rev. 3
5 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
5 Page 
White Electronic Designs
W3EG7266S-D3
PRELIMINARY
ORDERING INFORMATION FOR D3
Part Number
Speed
CAS Latency
tRCD tRP
Height*
W3EG7266S262D3
133MHz/266Mbps
2
22
26.67 (1.05")
W3EG7266S265D3
133MHz/266Mbps
2.5
33
26.67 (1.05")
W3EG7266S202D3
100MHz/200Mbps
2
22
26.67 (1.05")
NOTES:
• Consult Factory for availability of RoHS compliant products. (G = RoHS Compliant)
• Vendor specific part numbers are used to provide memory components source control. The place holder for this is shown as lower case “x” in the part numbers above and is to
be replaced with the respective vendors code. Consult factory for qualified sourcing options. (M = Micron, S = Samsung & consult factory for others)
• Consult factory for availability of industrial temperature (-40°C to 85°C) option
PACKAGE DIMENSIONS FOR D3
3.99
(0.157)
(4X)
17.78
(0.700)
10.01
(0.394)
6.35
(0.250)
133.48
(5.255)
MAX
64.77
(2.550)
6.35
(0.250)
1.78
(0.070)
26.67
(1.050)
MAX
3.99
(0.157)
MAX
4.06
(0.160)
MAX
1.27 (0.050) TYP
49.53
(1.950)
3.00
(0.118)
(4X)
1.27 ± 0.10
(0.050 ± 0.004)
* ALL DIMENSIONS ARE IN MILLIMETERS AND (INCHES).
October 2005
Rev. 3
11 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
11 Page | ||
| Páginas | Total 12 Páginas | |
| PDF Descargar | [ Datasheet W3EG7266S-D3.PDF ] | |
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