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HI-8785 PDF даташит

Спецификация HI-8785 изготовлена ​​​​«Holt Integrated Circuits» и имеет функцию, называемую «(HI-8783 - HI-8785) 8 bit parallel data converted to 429 & 561 serial data out».

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Номер произв HI-8785
Описание (HI-8783 - HI-8785) 8 bit parallel data converted to 429 & 561 serial data out
Производители Holt Integrated Circuits
логотип Holt Integrated Circuits логотип 

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HI-8785 Даташит, Описание, Даташиты
HI-8783, HI-8784, HI-8785
ARINC INTERFACE DEVICE
September 2006 8 bit parallel data converted to 429 & 561 serial data out
DESCRIPTION
The HI-8783, HI-8784, and HI-8785 are system compo-
nents for interfacing 8 bit parallel data to an ARINC 429
bus. The HI-8783 is a logic device only and requires a sep-
arate line driver circuit, such as the HI-3182 or HI-8585.
The HI-8784 and HI-8785 combine logic and line driver on
one chip. The HI-8784 has an output resistance of 37.5
ohms, and the HI-8785 has an output resistance of 10
ohms to facilitate external lightning protection cicuitry. The
technology is analog/digital CMOS.
The HI-8783 is available in a 22 pin DIP format as a second
source replacement for the Micrel / California Devices
DLS-111BV.
The products offer high speed data bus data transactions
to a buffer register. After loading 4 bytes, data is automati-
cally transferred and transmitted. The data rate is equal to
the clock rate. Parity can be enabled in the 32nd bit. Reset
is used to initialize the logic upon startup. Word gaps are
transmitted automatically.
www.DataSheet4U.com
The HI-8784 and HI-8785 require +/- 10 volt supplies in ad-
dition to the 5 volt supply.
PIN CONFIGURATIONS
VCC 1
20 561 DATA
561 SYNC 2
19 DATA ZERO
D0 3
18 DATA ONE
D1 4 HI-8783PSI 17 PARITY ENB
&
D2 5 HI-8783PST 16 XMT READY
D3 6
15 XMIT CLK
D4 7
14 RESET
D5 8
13 WRITE
D6 9
12 A0
D7 10
11 GND
20-Pin Plastic SOIC - WB package
FEATURES
l Automatically converts 8 bit parallel data
to ARINC 429 or 561 serial data
l High speed data bus interface
l On-chip line driver option
l SOIC packages available
l Military processing options
VCC 1
561 SYNC 2
D0 3
D1 4
D2 5
D3 6
D4 7
D5 8
D6 9
NC 10
D7 11
GND 12
HI-8784PSI
HI-8784PST
HI-8785PSI
&
HI-8785PST
24 V+
23 561 DATA
22 TXBOUT
21 TXAOUT
20 V-
19 PARITY ENB
18 XMT READY
17 XMIT CLK
16 RESET
15 WRITE
14 SLP1.5
13 A0
24-Pin Plastic SOIC - WB package
(See page 7 for additional pin configurations)
(DS8783 Rev.I)
HOLT INTEGRATED CIRCUITS
www.holtic.com
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HI-8785 Даташит, Описание, Даташиты
HI-8783, HI-8784, HI-8785
PIN DESCRIPTIONS
PIN PIN PIN SYMBOL FUNCTION
HI-8783 HI-8783 HI-8784
(20-pin) (22-pin) HI-8785
DESCRIPTION
1
2
3-10
11
12
-
13
14
15
16
17
-
18
19
-
-
20
-
22
1
2-8,10
11
12
-
14
15
16
17
18
-
19
20
-
-
21
-
1
2
3-9,11
12
13
14
15
16
17
18
19
20
-
-
21
22
23
24
VCC
power supply +5 volt rail,
561 SYNC digital output ARINC 561 Sync signal
Dn digital inputs Parallel 8 bit Data Input
GND
power supply Ground
A0 digital input Byte address, A0=1 for 1st byte, A0=0 for 2nd, 3rd & 4th bytes
SLP1.5 digital input Selects the slope of the line driver. High = 1.5us
WRITE digital input Write strobe, loads data on rising edge
RESET digital input Registers and sequencing logic initialized when low
XMIT CLK digital input Clock input for the transmitter
XMT RDY digital output Goes high if the buffer register is empty
PARITY ENB digital input When high the 32nd bit output is odd parity
V- power supply -10 volt rail
DATA ONE digital output Goes high for each ARINC bit output that is a “one”
DATA ZERO digital output Goes high for each ARINC bit output that is a “zero”
TXAOUT analog output Line driver ouptut - A side
TXBOUT analog output Line driver output - B side
561 DATA digital output Serial output for ARINC 561 data
V+ power supply +10 volt rail
FUNCTIONAL DESCRIPTION
The HI-8783 is a parallel to serial converter, which when
loaded with four eight bit parallel bytes, outputs the data as a
32 bit serial word. Timing circuitry inserts a 4 bit gap at the
end of each 32 bit word. An input buffer register allows load
operations to take place while the previously loaded word is
being transmitted.
If the PARITY ENB pin is high, the 32nd bit will be a parity bit,
inserted so as to make the 32 bit word have odd parity. If the
PARITY ENB pin is low, the 32nd bit will be the D7 bit of the
4th byte.
Outputs are provided for both ARINC 429/575 (DATA ONE
and DATA ZERO pins) and ARINC 561 (561 DATA and 561
SYNC pins) type data.
A low signal applied to the RESET pin resets the HI-8783’s
internal logic so that spurious transmission does not take
place during power-up. The registers are cleared so that a
continuous gap will be transmitted until the first word is
loaded into the transmitter.
Input data can be loaded when the XMT RDY signal is high,
which indicates the input buffer register is empty. The first 8
bit byte is the label byte and is loaded with the A0 input high,
which initializes the internal byte counter. The remaining
three bytes are loaded with A0 in the low state. Once A0 is
set low, it must not go high until after the fourth byte is loaded.
Each 8 bit byte is loaded into the input buffer register by a low
pulse on the WRITE input. After the fourth byte is loaded, the
XMT RDY output goes low.
The contents of the input buffer register are transferred to the
output register during the fourth bit period of the gap. If the
fourth gap bit period of the previous word has already been
transmitted, the contents of the input buffer register will be
transferred to the output shift register during the first bit pe-
riod after the loading of the fourth byte, and the XMT RDY out-
put goes high.
After the output shift register is loaded, the data is shifted out
to the output logic in the order shown in figure 2.
The 561 SYNC output pulses low when the XMT CLK is low
during the 8th bit of the ARINC transmission.
The XMIT CLK is the same as the data rate.
HOLT INTEGRATED CIRCUITS
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HI-8785 Даташит, Описание, Даташиты
HI-8783, HI-8784, HI-8785
WRITE
A0
byte
counter
XMIT CLK
status &
control
logic
DATA
8
BUS
8 to 32 bit
mux
32
32 bit
buffer
register
32
32 bit
shift
register
SLP1.5
XMT RDY
word gap
counter
bit
counter
line
driver
TXAOUT
TXBOUT
HI-8784, HI8785
output
logic
DATA ONE
DATA ZERO
HI-8783
561 SYNC
561 DATA
PARITY ENB
Figure 1. Block Diagram
FUNCTIONAL DESCRIPTION (Cont.) A0 Byte Data Bus
ARINC Bits
The HI-8784 and HI-8785 have the same digital logic func-
tion as the HI-8783, but include an on-chip line driver de-
signed to directly drive the ARINC 429 bus. The two ARINC
outputs (TXAOUT and TXBOUT) provide a differential volt-
age to produce a +10 volt One, a -10 volt Zero, and a 0 volt
Null. The slope of the ARINC outputs is controlled by the
SLP1.5 pin. If SLP1.5 is high, the output rise and fall time is
nominally 1.5us. If SLP1.5 is set low, the rise and fall times
are 10us. DATA ONE and DATA ZERO outputs are not pro-
vided for the HI-8784 and HI-8785.
1 Byte 1 D0 - D7
0 Byte 2 D0 - D7
0 Byte 3 D0 - D7
0 Byte 4 D0 - D7
ARINC 1 - ARINC 8
ARINC 9 - ARINC 16
ARINC 17 - ARINC 24
ARINC 25 - ARINC 32
Figure 2. Order of transmitted bytes
POWER SUPPLY SEQUENCING
The HI-8784 has 37.5 ohms in series with each line driver out-
put. The HI-8785 has 10.0 ohms in series. The HI-8785 is for
applications where external series resistance is needed, typi-
cally for lightning protection devices.
The power supplies must be controlled to prevent large
currents during supply turn-on and turn-off. The required
sequence is V+ followed by VDD, always ensuring that V+ is
the most positive supply. The V- supply is not critical and can
be asserted at any time.
HOLT INTEGRATED CIRCUITS
3










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