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PDF 74HC4852 Data sheet ( Hoja de datos )
| Número de pieza | 74HC4852 | |
| Descripción | Dual 4-channel analog multiplexer/demultiplexer | |
| Fabricantes | NXP Semiconductors | |
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74HC4852
Dual 4-channel analog multiplexer/demultiplexer with
injection-current effect control
Rev. 02 — 30 May 2007
Product data sheet
1. General description
www.DataSheet4U.com
2. Features
The 74HC4852 is a high-speed Si-gate CMOS device and is specified in compliance with
JEDEC standard no. 7A.
The 74HC4852 is a dual 4-channel analog multiplexer or demultiplexer with common
select inputs (S0 and S1). Both multiplexers have a common active LOW enable input (E),
four independent inputs/outputs (pins nY0 to nY3) and a common input/output (pin nZ).
The device features injection-current effect control, which has excellent value in
automotive applications where voltages in excess of the supply voltage are common.
With E LOW, two of the eight switches are selected (low impedance ON-state) by S0 and
S1. With E HIGH, all switches are in the high-impedance OFF-state, independent of S0
and S1.
The injection-current effect control allows signals at disabled analog input channels to
exceed the supply voltage without affecting the signal of the enabled analog channel. This
eliminates the need for external diode/resistor networks typically used to keep the analog
channel signals within the supply-voltage range.
I Injection-current cross coupling < 1 mV/mA
I Wide supply voltage range from 2.0 V to 6.0 V
I ESD protection:
N HBM JESD22-A114E Class 2 exceeds 2000 V
N MM JESD22-A115-A exceeds 200 V
N CDM JESD22-C101C exceeds 1000 V
I Latch-up performance exceeds 100 mA per JESD 78 Class II
I Low ON-state resistance:
N 400 Ω (typical) at VCC = 2.0 V
N 215 Ω (typical) at VCC = 3.0 V
N 120 Ω (typical) at VCC = 3.3 V
N 76 Ω (typical) at VCC = 4.5 V
N 59 Ω (typical) at VCC = 6.0 V
1 page  
NXP Semiconductors
74HC4852
4-channel analog MUX/DEMUX with injection-current effect control
7. Functional description
Table 3. Function table[1]
Input
Channel ON
E S1 S0
L L L nY0 to nZ
L L H nY1 to nZ
L H L nY2 to nZ
L H H nY3 to nZ
HXX-
[1] H = HIGH voltage level;
L = LOW voltage level;
X = don’t care.
8. Limiting values
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
Parameter
Conditions
Min Max
Unit
VCC
VI
VSW
IIK
ISK
ISW
ICC
IGND
Tstg
Ptot
supply voltage
input voltage
switch voltage
input clamping current
switch clamping current
switch current
supply current
ground current
storage temperature
total power dissipation
enable and disable mode
VI < 0 V or VI > VCC
VI < 0 V or VI > VCC
VSW = 0 V to VCC
Tamb = −40 °C to +125 °C
−0.5
−0.5
−0.5
-
-
-
-
−50
−65
[1] -
+7.0
VCC + 0.5
VCC + 0.5
±20
±20
±25
50
-
+150
500
V
V
V
mA
mA
mA
mA
mA
°C
mW
[1] For SO16 package: Ptot derates linearly with 8 mW/K above 70 °C.
For TSSOP16 package: Ptot derates linearly with 5.5 mW/K above 60 °C.
For DHVQFN16 packages: Ptot derates linearly with 4.5 mW/K above 60 °C.
74HC4852_2
Product data sheet
Rev. 02 — 30 May 2007
© NXP B.V. 2007. All rights reserved.
5 of 20
5 Page 
NXP Semiconductors
74HC4852
4-channel analog MUX/DEMUX with injection-current effect control
11. Dynamic characteristics
Table 9. Dynamic characteristics
GND = 0 V; CL = 50 pF; RL = 10 kΩ unless specified otherwise; for test circuit see Figure 12.
Symbol Parameter
Conditions
25 °C
−40 °C to +85 °C −40 °C to +125 °C Unit
Min Typ Max Min Max Min Max
VCC = 2.0 V
tpd propagation delay see Figure 10
[1]
nZ, nYn to nYn, nZ
2.2 9.3 33 2.2
34
2.2
35 ns
Sn to nZ, nYn
7.7 16.8 38 6.3
40
6.3
42 ns
ten enable time see Figure 11
E to nZ, nYn
[2]
10.5 20.5 47.5 8.5 52.5 8.5 57.5 ns
tdis disable time see Figure 11
E to nZ, nYn
[3]
39.5 75.4 100 39.3 105 39 115 ns
VCC = 3.0 V
tpd propagation delay see Figure 10
[1]
nZ, nYn to nYn, nZ
2.2 4.9 16.5 1.9 18 1.9 19.5 ns
Sn to nZ, nYn
4.9 8.8 20 3.9 21.5
3.9
23 ns
ten enable time see Figure 11
E to nZ, nYn
[2]
6.2 10.6 45 5.2
50
5.2
55 ns
tdis disable time see Figure 11
E to nZ, nYn
[3]
35.2 69.5 90 35.5 100 35 110 ns
VCC = 3.3 V
tpd propagation delay see Figure 10
[1]
nZ, nYn to nYn, nZ
2.0 4.4 15.0 1.6 16.5 1.6 18.5 ns
Sn to nZ, nYn
4.4 7.9 17.5 3.4
19
3.4
22 ns
ten enable time see Figure 11
E to nZ, nYn
[2]
5.6 9.4 42.5 4.6 47.5 4.6 52.5 ns
tdis disable time see Figure 11
E to nZ, nYn
[3]
34.6 68.1 85 34.6 95 34.5 105 ns
VCC = 4.5 V
tpd propagation delay see Figure 10
[1]
nZ, nYn to nYn, nZ
1.6 3.2 11.6 1.1 12.5 1.1 13.5 ns
Sn to nZ, nYn
3.2 5.8 14 2.3
15
2.3
17 ns
ten enable time see Figure 11
E to nZ, nYn
[2]
4.2 6.9 40
3
45
3
50 ns
tdis disable time see Figure 11
E to nZ, nYn
[3]
28.5 63 80 28.2
90
28
100 ns
74HC4852_2
Product data sheet
Rev. 02 — 30 May 2007
© NXP B.V. 2007. All rights reserved.
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