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Número de pieza | NTD50N03R | |
Descripción | Power MOSFET ( Transistor ) | |
Fabricantes | ON Semiconductor | |
Logotipo | ||
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No Preview Available ! NTD50N03R
Power MOSFET
25 V, 45 A, Single N−Channel, DPAK
Features
• Planar Technology
• Low RDS(on) to Minimize Conduction Losses
• Low Capacitance to Minimize Driver Losses
• Optimized Gate Charge to Minimize Switching Losses
• Pb−Free Packages are Available
Applications
• VCORE DC−DC Buck Converter Applications
• Optimized for High Side Switching
MAXIMUM RATINGS (TJ = 25°C unless otherwise noted)
Parameter
Symbol Value
Unit
Drain−to−Source Voltage
Gate−to−Source Voltage
Continuous Drain
Current (RqJA)
(Note 1)
TA = 25°C
TA = 85°C
VDSS
VGS
ID
25
"20
9.2
7.2
V
V
A
Power Dissipation
(RqJA) (Note 1)
Continuous Drain
Current (RqJA)
(Note 2)
Power Dissipation
(RqJA) (Note 2)
Continuous Drain
Current (RqJC)
(Note 1)
TA = 25°C
Steady
State
TA = 25°C
TA = 85°C
TA = 25°C
TC = 25°C
TC = 85°C
PD
ID
PD
ID
2.1 W
7.8 A
6.0
1.5 W
45 A
35
Power Dissipation
(RqJC) (Note 1)
Pulsed Drain Current
Current Limited by
Package
TC = 25°C
PD
TA = 25°C,
tp = 10 ms
TA = 25°C
IDM
IDmaxPkg
50
180
45
W
A
A
Operating Junction and Storage
Temperature
TJ, Tstg
−55 to
175
°C
Source Current (Body Diode)
Drain−to−Source (dv/dt)
IS
dv/dt
45 A
8.0 V/ns
Single Pulse Drain−to−Source Avalanche
Energy (TJ = 25°C, VDD = 50 V, VGS = 10 V,
IL = 6.32 Apk, L = 1.0 mH, RG = 25 W)
Lead Temperature for Soldering Purposes
(1/8″ from case for 10 s)
EAS
TL
20 mJ
260 °C
Stresses exceeding Maximum Ratings may damage the device. Maximum
Ratings are stress ratings only. Functional operation above the Recommended
Operating Conditions is not implied. Extended exposure to stresses above the
Recommended Operating Conditions may affect device reliability.
1. Surface−mounted on FR4 board using 1 sq in pad, 1 oz Cu.
2. Surface−mounted on FR4 board using the minimum recommended pad size.
http://onsemi.com
V(BR)DSS
25 V
RDS(on) TYP
12.5 mW @ 10 V
19 mW @ 4.5 V
N−Channel
D
ID MAX
45 A
G
S
44
4
12
3
CASE 369AA
DPAK
(Surface Mount)
STYLE 2
1
2
3
CASE 369D
DPAK
(Straight Lead)
STYLE 2
1 23
CASE 369AC
3 IPAK
(Straight Lead)
MARKING DIAGRAMS
& PIN ASSIGNMENTS
4
Drain
4
Drain
2
1 Drain 3
Gate
Source
13
Gate 2 Source
Drain
Y
WW
T50N03R
G
= Year
= Work Week
= Device Code
= Pb−Free Package
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 6 of this data sheet.
© Semiconductor Components Industries, LLC, 2007
March, 2007 − Rev. 4
1
Publication Order Number:
NTD50N03R/D
1 page NTD50N03R
1000
Ciss
800
VDS = 0 V VGS = 0 V
Crss
600
TJ = 25°C
Ciss
400
Coss
200
Crss
0
10
5 VGS 0 VDS 5
10 15 20
GATE−TO−SOURCE OR DRAIN−TO−SOURCE VOLTAGE
(VOLTS)
Figure 7. Capacitance Variation
16 16
12
VDS
8
QT
12
VGS
8
QGS
4
0
02
QGD
46
4
ID = 30 A
TJ = 25°C
0
8 10 12 14 16
Qg, TOTAL GATE CHARGE (nC)
Figure 8. Gate−to−Source and
Drain−to−Source Voltage versus Total Charge
100
VDS = 10 V
ID = 10 A
VGS = 10 V
tr
td(off)
10
td(on)
tf
1
1 10 100
RG, GATE RESISTANCE (W)
Figure 9. Resistive Switching Time Variation
versus Gate Resistance
20
18 VGS = 0 V
16 TJ = 25°C
14
12
10
8
6
4
2
0
0 0.2 0.4 0.6 0.8 1.0
VSD, SOURCE−TO−DRAIN VOLTAGE (VOLTS)
Figure 10. Diode Forward Voltage versus
Current
1000
SINGLE PULSE
VGS = 20 V
TC = 25°C
100
10 ms
100 ms
10
1 ms
1
0.1
RDS(on) LIMIT
THERMAL LIMIT
PACKAGE LIMIT
1
10
10 ms
dc
100
VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
Figure 11. Maximum Rated Forward Biased
Safe Operating Area
http://onsemi.com
5
5 Page |
Páginas | Total 8 Páginas | |
PDF Descargar | [ Datasheet NTD50N03R.PDF ] |
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NTD50N03R | Power MOSFET ( Transistor ) | ON Semiconductor |
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