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OX12PCI840 PDF даташит

Спецификация OX12PCI840 изготовлена ​​​​«Oxford Semiconductor» и имеет функцию, называемую «Integrated Parallel Port and PCI interface».

Детали детали

Номер произв OX12PCI840
Описание Integrated Parallel Port and PCI interface
Производители Oxford Semiconductor
логотип Oxford Semiconductor логотип 

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OX12PCI840 Даташит, Описание, Даташиты
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FEATURE
IEEE1284 SPP/EPP/ECP parallel port
Single function target PCI controller, fully PCI 2.2 and
PCI Power Management 1.0 compliant
2 multi-purpose IO pins which can be configured as
interrupt input pins
DESCRIPTION
The OX12PCI840 is a single chip solution for PCI-based
parallel expansion add-in cards. It is a single function PCI
device.
For legacy applications the PCI resources are arranged so
that the parallel port can be located at standard I/O
addresses.
The efficient 32-bit, 33MHz target-only PCI interface is
compliant with version 2.2 of the PCI Bus Specification and
OX12PCI840
Integrated Parallel Port
and PCI interface
Can be reconfigured using optional non-volatile
configuration memory (EEPROM)
5.0V operation
100 pin PQFP package
version 1.0 of PCI Power Management Specification. For
full flexibility, all the default register values can be
overwritten using an optional MicrowireTM serial EEPROM.
The OX12PCI840 provides an IEEE1284 EPP/ECP parallel
port which fully supports the existing Centronics interface.
Oxford Semiconductor Ltd.
25 Milton Park, Abingdon, Oxon, OX14 4SH, UK
Tel: +44 (0)1235 824900 Fax: +44(0)1235 821141
© Oxford Semiconductor 1999
OX12PCI840 1.2 – Dec 2001
Part No. OX12PCI840-PQC-A









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OX12PCI840 Даташит, Описание, Даташиты
OXFORD SEMICONDUCTOR LTD.
OX12PCI840
CONTENTS
1 PIN INFORMATION .....................................................................................................................4
2 PIN DESCRIPTIONS ....................................................................................................................5
3 CONFIGURATION & OPERATION ...............................................................................................8
4 PCI TARGET CONTROLLER .......................................................................................................9
4.1 OPERATION.......................................................................................................................................................................... 9
4.2 CONFIGURATION SPACE................................................................................................................................................... 9
4.2.1 PCI CONFIGURATION SPACE REGISTER MAP ......................................................................................................... 10
4.3 ACCESSING LOGICAL FUNCTIONS................................................................................................................................ 11
4.3.1 PCI ACCESS TO PARALLEL PORT .............................................................................................................................. 11
4.4 ACCESSING LOCAL CONFIGURATION REGISTERS .................................................................................................... 12
4.4.1 LOCAL CONFIGURATION AND CONTROL REGISTER ‘LCC’ (OFFSET 0X00) ......................................................... 12
4.4.2 MULTI-PURPOSE I/O CONFIGURATION REGISTER ‘MIC’ (OFFSET 0X04)............................................................. 13
4.4.3 LOCAL BUS TIMING PAR AMETER REGISTER 1 ‘LT1’ (OFFSET 0X08): ................................................................... 13
4.4.4 LOCAL BUS TIMING PAR AMETER/BAR SIZING REGISTER 2 ‘LT2’ (OFFSET 0X0C):............................................. 14
4.4.5 GLOB AL INTERRUPT STATUS AND CONTROL REGISTER ‘GIS’ (OFFSET 0X10) ................................................. 15
4.5 PCI INTERRUPTS ............................................................................................................................................................... 16
4.6 POWER MANAGEMENT.................................................................................................................................................... 17
4.6.1 POWER MANAGEMENT USING MIO............................................................................................................................ 17
5 BI-DIRECTIONAL PARALLEL PORT..........................................................................................18
5.1 OPERATION AND MODE SELECTION............................................................................................................................. 18
5.1.1 SPP MODE ...................................................................................................................................................................... 18
5.1.2 PS2 MODE ...................................................................................................................................................................... 18
5.1.3 EPP MODE ...................................................................................................................................................................... 18
5.1.4 ECP MODE ...................................................................................................................................................................... 18
5.2 PARALLEL PORT INTERRUPT ......................................................................................................................................... 18
5.3 REGISTER DESCRIPTION................................................................................................................................................. 19
5.3.1 PARALLEL PORT DATA REGISTER ‘PDR’................................................................................................................... 19
5.3.2 ECP FIFO ADDRESS / RLE ........................................................................................................................................... 19
5.3.3 DEVICE STATUS REGISTER ‘DSR’.............................................................................................................................. 19
5.3.4 DEVICE CONTROL REGISTER ‘DCR’ .......................................................................................................................... 20
5.3.5 EPP ADDRESS REGISTER ‘EPPA’ ............................................................................................................................... 20
5.3.6 EPP DATA REGISTERS ‘EPPD1-4’ ............................................................................................................................... 20
5.3.7 ECP DATA FIFO............................................................................................................................................................. 20
5.3.8 TEST FIFO...................................................................................................................................................................... 20
5.3.9 CONFIGURATION A REGISTER ................................................................................................................................... 20
5.3.10 CONFIGURATION B REGISTER ................................................................................................................................... 21
5.3.11 EXTENDED CONTROL REGISTER ‘ECR’ .................................................................................................................... 21
6 SERIAL EEPROM...................................................................................................................... 22
6.1 SPECIFICATION ................................................................................................................................................................. 22
6.2 EEPROM DATA ORGANISATION ..................................................................................................................................... 22
6.2.1 ZONE0: HEADER............................................................................................................................................................ 22
6.2.2 ZONE1: LOCAL CONFIGURATION REGISTERS ......................................................................................................... 23
6.2.3 ZONE2: IDENTIFICATION REGISTERS........................................................................................................................ 23
6.2.4 ZONE3: PCI CONFIGURATION REGISTERS ............................................................................................................... 23
6.2.5 ZONE4: FUNCTION ACCESS........................................................................................................................................ 25
7 OPERATING CONDITIONS ........................................................................................................26
Data Sheet Revision 1.2
Page 2









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OX12PCI840 Даташит, Описание, Даташиты
OXFORD SEMICONDUCTOR LTD.
OX12PCI840
8 DC ELECTRICAL CHARACTERISTICS ...................................................................................... 26
8.1 NON-PCI I/O BUFFERS ...................................................................................................................................................... 26
8.2 PCI I/O BUFFERS ............................................................................................................................................................... 27
9 AC ELECTRICAL CHARACTERISTICS ...................................................................................... 28
9.1 PCI BUS............................................................................................................................................................................... 28
10 TIMING WAVEFORMS............................................................................................................29
11 PACKAGE DETAILS .............................................................................................................. 30
12 NOTES ..................................................................................................................................31
13 CONTACT DETAILS...............................................................................................................32
Data Sheet Revision 1.2
Page 3










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Номер в каталогеОписаниеПроизводители
OX12PCI840Integrated Parallel Port and PCI interfaceOxford Semiconductor
Oxford Semiconductor

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