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PDF OXCB950 Data sheet ( Hoja de datos )

Número de pieza OXCB950
Descripción Integrated High Performance UART Cardbus / 3.3v PCI interface
Fabricantes Oxford Semiconductor 
Logotipo Oxford Semiconductor Logotipo



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FEATURES
OXCB950 DATASHEET
Integrated High Performance UART
Cardbus / 3.3v PCI interface
DS_B005A_00
Single high-performance UART channel
Cardbus/3.3v PCI compliant, single-function target
controller. Fully compliant to PC Card Standards,
and PCI Bus Specification 2.2, Power Management
1.0
Function access to preconfigure the UART prior to
handover to generic device drivers
UART fully software compatible with 16C550-type
devices.
Baud rates up to 15Mbps in asynchronous mode and
60Mbps in external 1x clock mode
128-byte deep FIFO per transmitter and receiver
Flexible clock prescaler from 1 to 31.875
Automated in-band flow control using programmable
Xon/Xoff in both directions
Automated out-of-band flow control using CTS#/RTS#
and/or DSR#/DTR#
Arbitrary trigger levels for receiver and transmitter
FIFO interrupts and automatic in-band and out-of-
band flow control
Infra-red (IrDA) receiver and transmitter operation
9-bit data framing as well as 5,6,7 and 8
Global Interrupt Status and readable FIFO levels to
facilitate implementation of efficient device drivers
Detection of bad data in the receiver FIFO
Operation via IO or memory mapping.
2 multi-purpose I/O pins which can be configured as
interrupt input or ‘wake-up’ pins
Auto-detection of optional MicrowireTM EEPROM, to
reconfigure device
3.3V operation
100 pin TQFP package
DESCRIPTION
The OXCB950 is a single chip UART solution for either
cardbus or PCI-based serial add-in cards. It is a single
function device, offering memory or IO mapped access to
the ultra-high performance 950-type UART.
This UART is the fastest available PC-compatible UART,
offering data rates up to 15Mbps and 128-byte deep
transmitter and receiver FIFOs. The deep FIFOs reduce
CPU overhead and allow utilisation of higher data rates.
The UART is software compatible with the widely used
industry-standard 16C550 devices and compatibles, as
well as the OX16C95x family of high performance UARTs.
In addition to increased performance and FIFO size, the
UART also provides the full set of OX16C95x enhanced
features including automated in-band flow control, readable
FIFO levels etc.
A set of local registers is available to enhance device driver
efficiency and reduce interrupt latency. The internal UART
has features such as shadowed FIFO fill levels, an interrupt
source register and Good-Data Status, readable in one
DWORD register visible to logical function0 in IO space
and memory space.
The efficient 32-bit, 33MHz target-only interface is
compliant with both the cardbus sections of the PC CARD
Standards, and the PCI bus specifications version 2.2 and
version 1.0 of PCI Power Management Specification.
For full flexibility, all the default register values can be
overwritten using an optional MicrowireTM serial EEPROM.
This EEPROM can also be used to provide function access
to pre-configure the UART into enhanced modes prior to
any cardbus/PCI configuration accesses and before control
is handed to generic device drivers.
Oxford Semiconductor Ltd.
25 Milton Park, Abingdon, Oxon
External—Free Release
OX14 4SH, UK
Tel: +44 (0)1235 824900 Fax: +44(0)1235 821141
Oxford Semiconductor 2005
OXCB950 Datasheet DS-0033 Sep 05
Part Nos. OXCB950-TQC60-A
OXCB950-TQAG

1 page




OXCB950 pdf
OXFORD SEMICONDUCTOR LTD.
OXCB950
1 PERFORMANCE COMPARISON
Feature
Support for PCI Power Management
Zero wait-state read/write operation
No. of external interrupt source pins
DWORD access to UART Interrupt Source
Registers & FIFO Levels
Good-Data status
Full Plug and Play with external EEPROM
External 1x baud rate clock
Max baud rate in normal mode
Max baud rate in 1x clock mode
FIFO depth
Sleep mode
Auto Xon/Xoff flow
Auto CTS#/RTS# flow
Auto DSR#/DTR# flow
No. of Rx interrupt thresholds
No. of Tx interrupt thresholds
No. of flow control thresholds
Transmitter empty interrupt
Readable status of flow control
Readable FIFO levels
Clock prescaler options
Rx/Tx disable
Software reset
Device ID
9-bit data frames
RS485 buffer enable
Infra-red (IrDA)
OXCB950
yes
yes
2
yes
yes
yes
yes
15 Mbps
60 Mbps
128
yes
yes
yes
yes
128
128
128
yes
yes
yes
248
yes
yes
yes
yes
yes
yes
16C550 +
PCI Bridge
no
no
2
no
no
yes
no
115 Kbps
n/a
16
no
no
no
no
4
1
n/a
no
no
no
n/a
no
no
no
no
no
no
16C650 +
PCI Bridge
No
No
2
No
No
Yes
No
1.5 Mbps
n/a
64
Yes
Yes
Yes
No
4
4
4
No
No
No
2
No
No
No
No
No
Yes
Table 1: OXCB950 performance compared with PCI Bridge + generic UART combinations in PCI mode
1.1 Improvements of the OXCB950 over discrete solutions:
Improved access timing:
Access to the internal UART requires zero or one PCI wait states. A cardbus/PCI read transaction from the internal UART can
complete within five PCI clock cycles and a write transaction to the internal UART can complete within four PCI clock cycles.
Reduces interrupt latency:
The OXCB950 offers shadowed FIFO levels and Interrupt status registers of the internal UART, as well as general device
interrupt status, to reduce the device driver interrupt latency.
Power management:
The OXCB950 complies with the Cardbus Power Management Specification, given by the PC CARD standard release 7.0/7.1,
the PCI Power Management Specification 1.0 and the PC98/99 Power Management specifications, by offering the extended
DS-0033 Sep 05
External-Free Release
Page 5

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OXCB950 arduino
OXFORD SEMICONDUCTOR LTD.
OXCB950
Note 3: Power & Ground
There are several types of VDD and VSS in this design, providing not only power for the internal (core) and I/O pad area but also
special power lines to the dual mode cardbus/pci I/O buffers. These power rails are not connected internally.
This precaution reduces the effects of simultaneous switching outputs and undesirable RF radiation from the chip. Further
precaution is taken by segmenting the GND and VDD rails to isolate the PCI and UART pins.
Pinout Assignment
This device implements the “common” silicon requirements given in the PC Card Standard, release 7.x.
The pinouts for this device have been assigned specifically to align the cardbus signals to the cardbus connector without any
signal crossovers. Since the assignment of signal pins on the cardbus connector is in a different sequence than those on the PCI
connector (due to the limitations of the cardbus connector) then crossovers do occur in the PCI environment. The following signal
lines are affected for the PCI environment : SERR#, AD16, INTA, CLK, and RST#.
DS-0033 Sep 05
External-Free Release
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