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PDF HCPL0631 Data sheet ( Hoja de datos )
| Número de pieza | HCPL0631 | |
| Descripción | (HCPL06xx) High Speed-10 MBit/s Logic Gate Optocouplers | |
| Fabricantes | Fairchild Semiconductor | |
| Logotipo |  |
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www.DataSheet4U.com
July 2005
HCPL0600, HCPL0601, HCPL0611,
HCPL0630, HCPL0631, HCPL0661
High Speed-10 MBit/s Logic Gate Optocouplers
Single Channel: HCPL0600, HCPL0601, HCPL0611
Dual Channel: HCPL0630, HCPL0631, HCPL0661
Features
■ Compact SO8 package
■ Very high speed-10 MBit/s
■ Superior CMR
■ Fan-out of 8 over -40°C to +85°C
■ Logic gate output
■ Strobable output (single channel devices)
■ Wired OR-open collector
■ U.L. recognized (File # E90700)
■ VDE approval pending
Applications
■ Ground loop elimination
■ LSTTL to TTL, LSTTL or 5-volt CMOS
■ Line receiver, data transmission
■ Data multiplexing
■ Switching power supplies
■ Pulse transformer replacement
■ Computer-peripheral interface
Description
The HCPL06XX optocouplers consist of an AlGaAS LED, opti-
cally coupled to a very high speed integrated photo-detector
logic gate with a strobable output (single channel devices). The
devices are housed in a compact small-outline package. This
output features an open collector, thereby permitting wired OR
outputs. The HCPL0600 and HCPL0601 output consists of
bipolar transistors on a bipolar process while the HCPL0611,
HCPL0630 and HCPL0631 output consists of bipolar transistors
on a CMOS process for reduced power consumption. The cou-
pled parameters are guaranteed over the temperature range of -
40°C to +85°C. A maximum input signal of 5 mA will provide a
minimum output sink current of 13 mA (fan out of 8). An internal
noise shield provides superior common mode rejection.
Package Dimensions
0.164 (4.16)
0.144 (3.66)
Pin 1
0.202 (5.13)
0.182 (4.63)
0.143 (3.63)
0.123 (3.13)
0.019 (0.48)
0.010 (0.25)
0.006 (0.16)
0.021 (0.53)
0.011 (0.28)
0.008 (0.20)
0.003 (0.08)
0.050 (1.27)
TYP
0.244 (6.19)
0.224 (5.69)
Lead Coplanarity : 0.004 (0.10) MAX
NOTE
All dimensions are in inches (millimeters)
©2005 Fairchild Semiconductor Corporation
1
HCPL0600, HCPL0601, HCPL0611, HCPL0630, HCPL0631, HCPL0661 Rev. 1.0.1
www.fairchildsemi.com
1 page  
Transfer Characteristics (TA = -40°C to +85°C Unless otherwise specified.)
DC Characteristics
Test Conditions Symbol Min Typ**
High Level Output Current
Low Level Output Voltage
Input Threshold Current
(VCC = 5.5 V, VO = 5.5 V)
(IF = 250 µA, VE = 2.0 V) (Note 2)
(VCC = 5.5 V, IF = 5 mA)
(VE = 2.0 V, IOL = 13 mA) (Note 2)
(VCC = 5.5 V, VO = 0.6 V,
VE = 2.0 V, IOL = 13 mA)
IOH
VOL
IFT
Max
100
0.6
5
Unit
µA
V
mA
Isolation Characteristics (TA = -40°C to +85°C Unless otherwise specified.)
Characteristics
Test Conditions Symbol Min Typ** Max
Unit
Input-Output
Insulation Leakage Current
(Relative humidity = 45%)
(TA = 25°C, t = 5 s)
(VI-O = 3000 VDC)
(Note 11)
II-O
1.0* µA
Withstand Insulation Test Voltage
Resistance (Input to Output)
Capacitance (Input to Output)
(RH < 50%, TA = 25°C)
(Note 11) ( t = 1 min.)
(VI-O = 500 V) (Note 11)
(f = 1 MHz) (Note 11)
VISO
RI-O
CI-O
2500
1012
0.6
VRMS
Ω
pF
** All typical values are at VCC = 5 V, TA = 25°C
NOTES
1. The VCC supply to each optoisolator must be bypassed by a 0.1µF capacitor or larger. This can be either a ceramic or solid
tantalum capacitor with good high frequency characteristic and should be connected as close as possible to the package VCC and
GND pins of each device.
2. Enable Input - No pull up resistor required as the device has an internal pull up resistor.
3. tPLH - Propagation delay is measured from the 3.75 mA level on the HIGH to LOW transition of the input current pulse to the 1.5V
level on the LOW to HIGH transition of the output voltage pulse.
4. tPHL - Propagation delay is measured from the 3.75 mA level on the LOW to HIGH transition of the input current pulse to the 1.5V
level on the HIGH to LOW transition of the output voltage pulse.
5. tr - Rise time is measured from the 90% to the 10% levels on the LOW to HIGH transition of the output pulse.
6. tf - Fall time is measured from the 10% to the 90% levels on the HIGH to LOW transition of the output pulse.
7. tELH - Enable input propagation delay is measured from the 1.5V level on the HIGH to LOW transition of the input voltage pulse to
the 1.5V level on the LOW to HIGH transition of the output voltage pulse.
8. tEHL - Enable input propagation delay is measured from the 1.5V level on the LOW to HIGH transition of the input voltage pulse to
the 1.5V level on the HIGH to LOW transition of the output voltage pulse.
9. CMH - The maximum tolerable rate of rise of the common mode voltage to ensure the output will remain in the high state (i.e., VOUT
> 2.0 V). Measured in volts per microsecond (V/µs).
10. CML - The maximum tolerable rate of fall of the common mode voltage to ensure the output will remain in the low output state (i.e.,
VOUT < 0.8 V). Measured in volts per microsecond (V/µs).
11. Device considered a two-terminal device: Pins 1,2,3 and 4 shorted together, and Pins 5,6,7 and 8 shorted together.
5
HCPL0600, HCPL0601, HCPL0611, HCPL0630, HCPL0631, HCPL0661 Rev. 1.0.1
www.fairchildsemi.com
5 Page 
Pulse Gen.
tf = tr = 5 ns
ZO = 50 Ω
1
Input
Monitor
(IF)
47Ω
2
3
4
VCC 8
7
.1µf
Bypass
6
GND 5
+5V
Pulse Gen.
ZO = 50 Ω
tf = tr = 5 ns
IF
Input
RL Monitoring
Node
Output
(VO)
CL
RM
Test Circuit for HCPL0600,
HCPL0601 and HCPL0611
Dual Channel
1 VCC 8
27
36
45
GND
+5 V
RL
0.1µF
Bypass
Output VO
Monitoring
Node
CL*
Input
(I F)
tPHL
Output
(VO)
Output
(VO)
Test Circuit for HCPL0630,
HCPL0631 and HCPL0661
tf
I F = 7.5 mA
I F = 3.75 mA
tPLH
90%
10 %
1.5 V
tr
Fig. 21 Test Circuit and Waveforms for tPLH, tPHL, tr and tf.
Pulse
Generator
tr = 5ns
ZO = 50Ω
1
7.5 mA
2
3
4
Input
Monitor
(VE)
+5V
VCC
8
7
.1µf
bypass
6
5
GND
RL
Output
(VO)
CL
Input
(VE )
tEHL
Output
(VO)
Fig. 22 Test Circuit tEHL and tELH.
t ELH
3.0 V
1.5 V
1.5 V
11
HCPL0600, HCPL0601, HCPL0611, HCPL0630, HCPL0631, HCPL0661 Rev. 1.0.1
www.fairchildsemi.com
11 Page | ||
| Páginas | Total 17 Páginas | |
| PDF Descargar | [ Datasheet HCPL0631.PDF ] | |
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