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PDF W79E201 Data sheet ( Hoja de datos )
| Número de pieza | W79E201 | |
| Descripción | 8-BIT MICROCONTROLLER | |
| Fabricantes | Winbond | |
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W79E201 Data Sheet
Table of Contents-
8-BIT MICROCONTROLLER
1. GENERAL DESCRIPTION ......................................................................................................... 3
2. FEATURES ................................................................................................................................. 3
3. PIN CONFIGURATION ............................................................................................................... 4
4. PIN DESCRIPTION..................................................................................................................... 5
5. BLOCK DIAGRAM ...................................................................................................................... 6
6. FUNCTIONAL DESCRIPTION ................................................................................................... 7
7. MEMORY ORGANIZATION ....................................................................................................... 8
8. INSTRUCTION.......................................................................................................................... 32
8.1 Instruction Timing ......................................................................................................... 32
9. POWER MANAGEMENT.......................................................................................................... 38
10. INTERRUPTS ........................................................................................................................... 41
11. PROGRAMMABLE TIMERS/COUNTERS ............................................................................... 42
11.1 Timer/Counters 0 & 1.................................................................................................... 42
11.2 Timer/Counter 2............................................................................................................ 45
12. WATCHDOG TIMER................................................................................................................. 48
13. SERIAL PORT .......................................................................................................................... 51
13.1 Framing Error Detection ............................................................................................... 56
13.2 Multiprocessor Communications .................................................................................. 56
14. PULSE WIDTH MODULATED OUTPUTS (PWM) ................................................................... 58
15. ANALOG-TO-DIGITAL CONVERTER ...................................................................................... 60
16. TIMED ACCESS PROTECTION .............................................................................................. 63
17. H/W REBOOT MODE (BOOT FROM 4K BYTES OF LD FLASH EPROM)............................. 64
18. IN-SYSTEM PROGRAMMING ................................................................................................. 65
18.1 The Loader Program Locates at LD Flash EPROM Memory....................................... 65
18.2 The Loader Program Locates at AP Flash EPROM Memory....................................... 65
19. H/W WRITER MODE ................................................................................................................ 65
20. SECURITY BITS ....................................................................................................................... 66
21. THE PERFORMANCE CHARACTERISTIC OF ADC .............................................................. 67
21.1 The Differential Nonlinearity VS Output code............................................................... 67
21.2 The Integral Nonlinearity VS Output code .................................................................... 68
Publication Release Date: December 16, 2004
- 1 - Revision A2
1 page  
W79E201
4. PIN DESCRIPTION
SYMBOL
EA
TYPE
IH
DESCRIPTIONS
EXTERNAL ACCESS ENABLE: This pin forces the processor to execute out
of external ROM. It should be kept high to access internal ROM. The ROM
address and data will not be present on the bus if EA pin is high and the
program counter is within 16KB area. Otherwise they will be present on the
bus.
PSEN
PROGRAM STORE ENABLE: PSEN enables the external ROM data onto
O H the Port 0 address/data bus during fetch and MOVC operations. When
internal ROM access is performed, no PSEN strobe signal outputs from this
pin.
ALE
OH
ADDRESS LATCH ENABLE: ALE is used to enable the address latch that
separates the address from the data on Port 0.
RST
IL
RESET: A high on this pin for two machine cycles while the oscillator is
running resets the device.
XTAL1
I
CRYSTAL1: This is the crystal oscillator input. This pin may be driven by an
external clock.
XTAL2
O CRYSTAL2: This is the crystal oscillator output. It is the inversion of XTAL1.
VSS
P Digital GROUND: Ground potential
VDD
P Digital POWER SUPPLY: Supply voltage for operation.
AVDD
P Analog POWER SUPPLY: Supply analog voltage for operation.
AVSS
P GROUND: Analog Ground potential
Vref P Vref: Analog reference input maximum voltage for ADC
P0.0−P0.7
PORT 0: Port 0 is an open-drain bi-directional I/O port with internal pull-up
I/O D(H)
resister option that is enabled by setting bit 0 of P0R(8Fh) to logic high. This
port also provides a multiplexed low order address/data bus during accesses
to external memory.
P1.0−P1.7
I
PORT 1: Port 1 is an input port. Or with an 8-bit analog input port for ADC0-
ADC7(8 analog input channels) used.
P2.0−P2.7
I/O
PORT 2: Port 2 is a bi-directional I/O port with internal weakly pull-ups. This
port also provides the upper address bits for accesses to external memory.
P3.0−P3.7
I/O
PORT 3: Port 2 is a bi-directional I/O port with internal weakly pull-ups.
Function is the same as that of the standard 8052.
P4.0
I/O PORT 4: A bi-directional I/O port with internal with weakly pull-ups
TCK
I L TCK: JTAG test clock
TMS
I H TMS: JTAG Test Mode select
TDI I H TDI: JTAG Test Data In
TDO
O TDO: JTAG Test Data Out
* Note: TYPE P: Power, I: input, O: output, I/O: bi-directional, H: pull-high, L: pull-low, D: open drain.
Publication Release Date: December 16, 2004
- 5 - Revision A2
5 Page 
W79E201
Continued
BIT NAME
4-
3 GF1
2 GF0
1 PD
0 IDL
FUNCTION
Reserve
General purpose user flag.
General purpose user flag.
1: Setting this bit causes the Chip to go into the POWER DOWN mode. In this mode
all the clocks are stopped and program execution is frozen.
1: Setting this bit causes the Chip to go into the IDLE mode. In this mode the clocks
to the CPU are stopped, so program execution is frozen. But the clock to the serial
port, ADC, timer and interrupt blocks is not stopped, and these blocks continue
operating.
Timer Control
Bit: 7 6 5 4 3 2 1
TF1 TR1 TF0 TR0 IE1 IT1 IE0
Mnemonic: TCON
Address: 88h
0
IT0
BIT NAME
FUNCTION
Timer 1 overflow flag: This bit is set when Timer 1 overflows. It is cleared
7 TF1 automatically when the program does a timer 1 interrupt service routine. Software
can also set or clear this bit.
6
TR1
Timer 1 run control: This bit is set or cleared by software to turn timer/counter on or
off.
Timer 0 overflow flag: This bit is set when Timer 0 overflows. It is cleared
5 TF0 automatically when the program does a timer 0 interrupt service routine. Software
can also set or clear this bit.
4
TR0
Timer 0 run control: This bit is set or cleared by software to turn timer/counter on or
off.
Interrupt 1 Edge Detect: Set by hardware when an edge/level is detected on INT1 .
3 IE1 This bit is cleared by hardware when the service routine is vectored to only if the
interrupt was edge triggered. Otherwise it follows the pin.
2
IT1
Interrupt 1 type control: Set/cleared by software to specify falling edge/ low level
triggered external inputs.
Interrupt 0 Edge Detect: Set by hardware when an edge/level is detected on INT0 .
1 IE0 This bit is cleared by hardware when the service routine is vectored to only if the
interrupt was edge triggered. Otherwise it follows the pin.
0
IT0
Interrupt 0 type control: Set/cleared by software to specify falling edge/ low level
triggered external inputs.
- 11 -
Publication Release Date: December 16, 2004
Revision A2
11 Page | ||
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