PDF NT5DS4M32EG Data sheet ( Hoja de datos )

Número de pieza	NT5DS4M32EG
Descripción	1M X 32 Bits X 4 Banks Double Data Rate Synchronous RAM
Fabricantes	NanoAmp Solutions
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No Preview Available ! www.DataSheet4U.com NanoAmp Solutions, Inc. 1982 Zanker Road, San Jose, CA 95112 ph: 408-573-8878, FAX: 408-573-8877 www.nanoamp.com NT5DS4M32EG Advance Information 1M × 32 Bits × 4 Banks Double Data Rate Synchronous RAM With Bi-Directional Data Strobe and DLL General Overview The NT5DS4M32EG is 134,217,728 bits of double data rate synchronous dynamic RAM organized as 4 x 1,048,576 bits by 32 I/Os. Synchronous features with Data Strobe allow extremely high performance up to 400Mbps/pin. I/O transactions are possible on both edges of the clock. Range of operating frequencies, programmable burst length and programmable latencies allow the device to be useful for a variety of high performance memory system applications. Features • VDD = 2.5V±5% , VDDQ = 2.5V±5% • SSTL_2 compatible inputs/outputs • 4 banks operation • MRS cycle with address key programs -CAS latency 2,3 (clock) -Burst length (2, 4, 8 and Full page) -Burst type (sequential & interleave) • Full page burst length for sequential burst type only • Start address of the full page burst should be even • All inputs except data & DM are sampled at the ris- ing edge of the system clock • Differential clock input(CK & /CK) • Data I/O transaction on both edges of Data strobe • 4 DQS (1 DQS/Byte) • DLL aligns DQ and DQS transaction with Clock transaction • Edge aligned data & data strobe output • Center aligned data & data strobe input • DM for write masking only • Auto & self refresh • 32ms refresh period (4K cycle) • 144-Ball FBGA package • Maximum clock frequency up to 200MHz • Maximum data rate up to 400Mbps/pin Ordering Information Part Number NT5DS4M32EG-5G NT5DS4M32EG-5 NT5DS4M32EG-6 Package 144-Balls Green FBGA Operating Temperature 0 - 70 °C Max. Frequency CL = 3 CL = 2 200MHz 200MHz 166MHz 111MHz - - Max Data Rate Interface 400Mbps/pin 400Mbps/pin 333Mbps/pin SSTL_2 Doc # 14-02-045 Rev A ECN 01-1118 The specifications of this device are subject to change without notice. For latest documentation see http://www.nanoamp.com. 1 1 page NanoAmp Solutions, Inc. Figure 3: SIMPLIFIED STATE DIAGRAM NT5DS4M32EG Advance Information MODE REGIST ER SET MRS POWER DOWN CKEL CKEH IDLE A CT REFRSEFSX SELF REFRESH REFA CKEL CKEH A UTO REFRESH POWER DOWN WRIT E ROW A CTIVE BST REA D WRIT EA REA DA WRIT E WRIT EA WRITE A WRIT E WRIT EA REA D REA DA REA D REA DA REA D A POWER A PPLIED POWER ON PRE PRE- CHA RGE Automatic Sequence Command Sequence WRITEA : Write with Autoprecharge READA : Read with Autoprecharge Doc # 14-02-045 Rev A ECN 01-1118 The specifications of this device are subject to change without notice. For latest documentation see http://www.nanoamp.com. 5 5 Page NanoAmp Solutions, Inc. Burst Interruption Read Interrupted by Read NT5DS4M32EG Advance Information Burst Read can be interrupted before completion of the burst by new Read command of any bank. When the previous burst is interrupted, the remaining address are overridden by the new address with the full burst length. The data from the previous Read command continues to appear on the outputs until the /CAS latency from the interrupting Read command is satisfied. Read to Read interval is minimum 1 tCK. Figure 10: Burst Interrupted by Read (Burst length = 4, /CAS Latency = 3) 0 1 23 4 5 67 8 /CK CK Command READ A READ B NOP NOP NOP NOP NOP NOP NOP /CAS Latency = 3 DQS DQ’s Douta0 Douta1 Doutb0 Doutb1 Doutb2 Doutb3 Read Interrupted by Burst stop & Write To interrupt Burst Read with a write command, Burst stop command must be asserted to avoid data contention on the I/O bus by placing the DQ’s(Output drivers) in a high impedance state at least one clock cycle before the Write Command is initiated. Once the burst stop command has been issued, the minimum delay to a write command is CL(RU). [CL is /CAS Latency and RU means round up to the nearest integer.] Figure 11: Burst Interrupted by Burst Stop & Write (Burst Length = 4, /CAS Latency = 3) 0 /CK CK Command READ /CAS Latency = 3 DQS DQ’s 1 Burst stop 2345 67 NOP NOP NOP t RPRE Preamble Dout0 Dout1 W RIT E NOP t DQSS t WPREH NOP t WPRES Din 0 Din 1 Din 2 Din 3 8 Doc # 14-02-045 Rev A ECN 01-1118 The specifications of this device are subject to change without notice. For latest documentation see http://www.nanoamp.com. 11 11 Page

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