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PDF 89HPES24N3A Data sheet ( Hoja de datos )
| Número de pieza | 89HPES24N3A | |
| Descripción | 24-Lane 3-Port PCI Express Switch | |
| Fabricantes | IDT | |
| Logotipo |  |
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24-Lane 3-Port
PCI Express® Switch
89HPES24N3A
Product Brief
Device Overview
The 89HPES24N3A is a member of the IDT PRECISE™ family of
PCI Express® switching solutions offering the next-generation I/O inter-
connect standard. The PES24N3A is a 24-lane, 3-port peripheral chip
that performs PCI Express Packet switching with a feature set optimized
for high performance applications such as servers, storage, and commu-
nications/networking. It provides high-performance I/O connectivity and
switching functions between a PCI Express upstream port and two
downstream ports or peer-to-peer switching between downstream ports.
The 89HPES24N3A offers an enhanced architecture and feature set
in a package that is pin-compatible with the first generation
89HPES24N3 24-lane, 3-port PCIe switch.
Features
◆ High Performance PCI Express Switch
– Twenty-four 2.5 Gbps PCI Express lanes
– Three switch ports
– Upstream port configurable up to x8
– Downstream ports configurable up to x8
– Low-latency cut-through switch architecture
– Support for Max Payload Size up to 2048 bytes
– One virtual channel
– Eight traffic classes
– PCI Express Base Specification Revision 1.1 compliant
◆ Flexible Architecture with Numerous Configuration Options
– Automatic per port link width negotiation to x8, x4, x2 or x1
– Automatic lane reversal on all ports
– Automatic polarity inversion on all lanes
– Ability to load device configuration from serial EEPROM
◆ Legacy Support
– PCI compatible INTx emulation
– Bus locking
◆ Highly Integrated Solution
– Requires no external components
– Incorporates on-chip internal memory for packet buffering and
queueing
– Integrates twenty-four 2.5 Gbps embedded SerDes with 8B/
10B encoder/decoder (no separate transceivers needed)
◆ Reliability, Availability, and Serviceability (RAS) Features
– Supports ECRC and Advanced Error Reporting
– Internal end-to-end parity protection on all TLPs ensures data
integrity even in systems that do not implement end-to-end
CRC (ECRC)
– Supports PCI Express Native Hot-Plug, Hot-Swap capable I/O
– Compatible with Hot-Plug I/O expanders used on PC and
server motherboards
Block Diagram
Frame Buffer
3-Port Switch Core
Route Table
Port
Arbitration
Scheduler
Transaction Layer
Data Link Layer
Multiplexer / Demultiplexer
Phy Phy
Logical Logical
Phy
Logical
Layer Layer ... Layer
SerDes SerDes
SerDes
Transaction Layer
Data Link Layer
Multiplexer / Demultiplexer
Phy Phy
Logical Logical
Phy
Logical
Layer Layer ... Layer
SerDes SerDes
SerDes
Transaction Layer
Data Link Layer
Multiplexer / Demultiplexer
Phy Phy
Logical Logical
Phy
Logical
Layer Layer ... Layer
SerDes SerDes
SerDes
© 2007 Integrated Device Technology, Inc.
24 PCI Express Lanes
x8 Upstream Port and Two x8 Downstream Ports
Figure 1 Internal Block Diagram
IDT and the IDT logo are trademarks of Integrated Device Technology, Inc.
1 of 2
February 8, 2007
1 page | ||
| Páginas | Total 2 Páginas | |
| PDF Descargar | [ Datasheet 89HPES24N3A.PDF ] | |
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