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89HPES48T12 PDF даташит

Спецификация 89HPES48T12 изготовлена ​​​​«IDT» и имеет функцию, называемую «48-Lane 12-Port PCI Express Switch».

Детали детали

Номер произв 89HPES48T12
Описание 48-Lane 12-Port PCI Express Switch
Производители IDT
логотип IDT логотип 

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48-Lane 12-Port
PCI Express® Switch
®
89HPES48T12
Data Sheet
Device Overview
The 89HPES48T12 is a member of the IDT PRECISE™ family of
PCI Express® switching solutions. The PES48T12 is a 48-lane, 12-port
peripheral chip that performs PCI Express packet switching with a
feature set optimized for high-performance applications such as servers,
storage, and communications/networking. It provides connectivity and
switching functions between a PCI Express upstream port and up to
eleven downstream ports and supports switching between downstream
ports.
Features
High Performance PCI Express Switch
– Twelve switch ports
Six main ports each of which consists of 8 SerDes
Each x8 main port can further bifurcate to 2 x4-ports
– Forty-eight 2.5 Gbps embedded SerDes
Supports pre-emphasis and receive equalization on per-port
basis
– Delivers 192 Gbps (24 GBps) of aggregate switching capacity
– Low-latency cut-through switch architecture
– Support for Max Payload Size up to 2048 bytes
– Supports one virtual channel and eight traffic classes
– PCI Express Base Specification Revision 1.1 compliant
Flexible Architecture with Numerous Configuration Options
– Port arbitration schemes utilizing round robin algorithms
– Automatic per port link width negotiation to x8, x4, x2 or x1
– Automatic lane reversal on all ports
– Automatic polarity inversion on all lanes
– Supports locked transactions, allowing use with legacy soft-
ware
– Ability to load device configuration from serial EEPROM
– Ability to control device via SMBus
Highly Integrated Solution
– Requires no external components
– Incorporates on-chip internal memory for packet buffering and
queueing
– Integrates forty-eight 2.5 Gbps embedded full duplex SerDes,
8B/10B encoder/decoder (no separate transceivers needed)
Reliability, Availability, and Serviceability (RAS) Features
– Redundant upstream port failover capability
– Supports optional PCI Express end-to-end CRC checking
Block Diagram
Route Table
Frame Buffer
x8/x4/x2/x1
SerDes
DL/Transaction Layer
Upstream
12-Port Switch Core
Port
Arbitration
Scheduler
DL/Transaction Layer
SerDes
DL/Transaction Layer
SerDes
DL/Transaction Layer
SerDes
DL/Transaction Layer
SerDes
DL/Transaction Layer
SerDes
x8/x4/x2/x1
x8/x4/x2/x1
x8/x4/x2/x1
x8/x4/x2/x1
48 PCI Express Lanes
Up to 6 x8 ports or 12 x4 Ports
Figure 1 Internal Block Diagram
x8/x4/x2/x1
© 2007 Integrated Device Technology, Inc.
IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc.
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89HPES48T12 Даташит, Описание, Даташиты
IDT 89HPES48T12 Data Sheet
– Internal end-to-end parity protection on all TLPs ensures data
integrity even in systems that do not implement end-to-end
CRC (ECRC)
– Supports optional PCI Express Advanced Error Reporting
– Supports PCI Express Hot-Plug
Compatible with Hot-Plug I/O expanders used on PC
motherboards
– Supports Hot-Swap
Power Management
– Supports PCI Power Management Interface specification,
Revision 1.1 (PCI-PM)
Supports powerdown modes at the link level (L0, L0s, L1,
L2/L3 Ready and L3) and at the device level (D0, D3hot)
– Unused SerDes disabled
Testability and Debug Features
– Built in SerDes Pseudo-Random Bit Stream (PRBS) generator
– Ability to read and write any internal register via the SMBus
– Ability to bypass link training and force any link into any mode
– Provides statistics and performance counters
32 General Purpose Input/Output pins
– Each pin may be individually configured as an input or output
– Each pin may be individually configured as an interrupt input
– Some pins have selectable alternate functions
Packaged in a 35mm x 35mm 1156-ball Flip Chip BGA with
1mm ball spacing
Product Description
Utilizing standard PCI Express interconnect, the PES48T12 provides
the most efficient connectivity solution for applications requiring high
throughput, low latency, and simple board layout with a minimum
number of board layers. It provides 192 Gbps of aggregated switching
capacity through 48 integrated serial lanes, using proven and robust IDT
technology. Each lane provides 2.5 Gbps of bandwidth in both directions
and is fully compliant with PCI Express Base specification 1.1.
The PES48T12 is based on a flexible and efficient layered architec-
ture. The PCI Express layers consist of SerDes, Physical, Data Link and
Transaction layers. The PES48T12 can operate either as a store and
forward switch or a cut-through switch and is designed to switch memory
and I/O transactions. It supports eight Traffic Classes (TCs) and one
Virtual Channel (VC) with sophisticated resource management to enable
efficient switching and I/O connectivity.
SMBus Interface
The PES48T12 contains two SMBus interfaces. The slave interface
provides full access to the configuration registers in the PES48T12,
allowing every configuration register in the device to be read or written
by an external agent. The master interface allows the default configura-
tion register values of the PES48T12 to be overridden following a reset
with values programmed in an external serial EEPROM. The master
interface is also used by an external Hot-Plug I/O expander.
Six pins make up each of the two SMBus interfaces. These pins
consist of an SMBus clock pin, an SMBus data pin, and 4 SMBus
address pins. In the slave interface, these address pins allow the SMBus
address to which the device responds to be configured. In the master
interface, these address pins allow the SMBus address of the serial
configuration EEPROM from which data is loaded to be configured. The
SMBus address is set up on negation of PERSTN by sampling the
corresponding address pins. When the pins are sampled, the resulting
address is assigned as shown in Table 1.
x8 2
3
Non-bifurcated
x8
10
45 67 89
x8 x8 x8
11 x8
10
x4 2
x4 3
Fully Bifurcated
x4 x4
1 0 11 x4
10 x4
456789
x4 x4 x4 x4 x4 x4
Figure 2 Port Configuration Examples
Note: The configurations in the above diagram show the maximum port widths. The PES48T12 can negotiate to narrower port widths — x4,
x2, or x1.
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IDT 89HPES48T12 Data Sheet
Slave
Master
Bit
SMBus
SMBus
Address
Address
1
SSMBADDR[1]
MSMBADDR[1]
2
SSMBADDR[2]
MSMBADDR[2]
3
SSMBADDR[3]
MSMBADDR[3]
4 0 MSMBADDR[4]
5 SSMBADDR[5]
1
61
0
71
1
Table 1 Master and Slave SMBus Address Assignment
As shown in Figure 3, the master and slave SMBuses may be used in a unified or split configuration. In the unified configuration, shown in Figure
3(a), the master and slave SMBuses are tied together and the PES48T12 acts both as a SMBus master as well as a SMBus slave on this bus. This
requires that the SMBus master or processor that has access to PES48T12 registers supports SMBus arbitration. In some systems, this SMBus
master interface may be implemented using general purpose I/O pins on a processor or micro controller, and may not support SMBus arbitration. To
support these systems, the PES48T12 may be configured to operate in a split configuration as shown in Figure 3(b).
In the split configuration, the master and slave SMBuses operate as two independent buses and thus multi-master arbitration is never required.
The PES48T12 supports reading and writing of the serial EEPROM on the master SMBus via the slave SMBus, allowing in system programming of
the serial EEPROM.
PES48T12
Processor
SMBus
Master
...Serial
EEPROM
Other
SMBus
Devices
PES48T12
...Processor
SMBus
Other
SMBus
Master
Devices
SSMBCLK
SSMBDAT
MSMBCLK
MSMBDAT
SSMBCLK
SSMBDAT
MSMBCLK
MSMBDAT
Serial
EEPROM
(a) Unified Configuration and Management Bus
(b) Split Configuration and Management Buses
Figure 3 SMBus Interface Configuration Examples
Hot-Plug Interface
The PES48T12 supports PCI Express Hot-Plug on each downstream port. To reduce the number of pins required on the device, the PES48T12
utilizes an external I/O expander, such as that used on PC motherboards, connected to the SMBus master interface. Following reset and configura-
tion, whenever the state of a Hot-Plug output needs to be modified, the PES48T12 generates an SMBus transaction to the I/O expander with the new
value of all of the outputs. Whenever a Hot-Plug input changes, the I/O expander generates an interrupt which is received on the IOEXPINTN input pin
(alternate function of GPIO) of the PES48T12. In response to an I/O expander interrupt, the PES48T12 generates an SMBus transaction to read the
state of all of the Hot-Plug inputs from the I/O expander.
General Purpose Input/Output
The PES48T12 provides 32 General Purpose I/O (GPIO) pins that may be individually configured as general purpose inputs, general purpose
outputs, or alternate functions. Some GPIO pins are shared with other on-chip functions. These alternate functions may be enabled via software,
SMBus slave interface, or serial configuration EEPROM.
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