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PDF 92HD71B5 Data sheet ( Hoja de datos )
| Número de pieza | 92HD71B5 | |
| Descripción | 4-CHANNEL HD AUDIO CODEC OPTIMIZED | |
| Fabricantes | IDT | |
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DATASHEET
4-CHANNEL HD AUDIO CODECS OPTIMIZED
FOR LOW POWER
92HD71B5
Description
The 92HD71B5 codec is a low power optimized, high
fidelity, 4-channel audio codec compatible with Intel’s High
Definition (HD) Audio Interface. The 92HD71B5 codec
provides stereo 24-bit resolution with sample rates up to
192kHz. Dual SPDIF provides connectivity to consumer
electronic equipment that is WLP complaint. The
92HD71B5 provides high quality, HD Audio capability to
notebook and business desktop PC applications.
Features
• 4 Channels (2 stereo DACs and 2 stereo ADCs) with
24-bit resolution
• Supports full-duplex stereo audio and simultaneous VoIP
• Provides a mono output for laptop sub-woofer
• Microsoft WLP 3/4 premium logo compliant, as
defined in WLP 3.09
• Optimized and flexible power management with
pop/click mitigation
• 2 independent S/PDIF Output converters for WLP
compliant HDMI/SPDIF support.
• Support for 1.5V and 3.3V HDA signaling with
runtime selection
• Digital microphone input (mono, stereo, or quad
array)
• 2 Adjustable VREF Out pins for microphone bias
• 4 analog ports
• Supports to 2 stereo microphone inputs
• Two-pin volume up/down control
• Digital PC Beep to all outputs
• Integrated headphone amp
• Jack insertion detection
• Sample rates up to 192kHz
• +3.3 V, +4 V, +4.75 V and +5 V analog power supply
options
• 48-pin QFP and 48-pad QFN RoHS packages
Preliminary Datasheet
Block Diagram
X
DUAL SPDIF
Port A
Port B
Port C
Port D
SPDIF Out 1
SPDIF Out 2
IDT™ CONFIDENTIAL AND PROPRIETARY
4-CHANNEL HD AUDIO CODECS OPTIMIZED FOR LOW POWER
1
92HD71B5
V 0.9 09/07
1 page  
92HD71B5
4-CHANNEL HD AUDIO CODECS OPTIMIZED FOR LOW POWER
PC AUDIO
8.8.3. DAC1 OutAmpLeft .............................................................................................................87
8.8.4. DAC1 OutAmpRight ...........................................................................................................88
8.8.5. DAC1 PwrState ..................................................................................................................88
8.8.6. DAC1 CnvtrID ....................................................................................................................89
8.8.7. DAC1 LR ............................................................................................................................89
8.9. ADC0 Node (NID = 12) ....................................................................................................................90
8.9.1. ADC0 WCap ......................................................................................................................90
8.9.2. ADC0 ConLst .....................................................................................................................91
8.9.3. ADC0 ConLstEntry0 ...........................................................................................................92
8.9.4. ADC0 Cnvtr ........................................................................................................................92
8.9.5. ADC0 ProcState .................................................................................................................93
8.9.6. ADC0 PwrState ..................................................................................................................94
8.9.7. ADC0 CnvtrID ....................................................................................................................94
8.10. ADC1 Node (NID = 13) ..................................................................................................................95
8.10.1. ADC1 WCap ....................................................................................................................95
8.10.2. ADC1 ConLst ...................................................................................................................96
8.10.3. ADC1 ConLstEntry0 .........................................................................................................96
8.10.4. ADC1 Cnvtr ......................................................................................................................97
8.10.5. ADC1 ProcState ...............................................................................................................98
8.10.6. ADC1 PwrState ................................................................................................................98
8.10.7. ADC1 CnvtrID ..................................................................................................................99
8.11. MonoOut Node (NID = 14) .............................................................................................................99
8.11.1. MonoOut WCap ...............................................................................................................99
8.11.2. MonoOut PinCap ...........................................................................................................101
8.11.3. MonoOut ConLst ............................................................................................................102
8.11.4. MonoOut ConLstEntry0 .................................................................................................102
8.11.5. MonoOut PinWCntrl .......................................................................................................103
8.11.6. MonoOut InAmpLeft .......................................................................................................103
8.11.7. MonoOut ConfigDefault .................................................................................................103
8.12. MonoMux Node (NID = 15) ..........................................................................................................105
8.12.1. MonoMux WCap ............................................................................................................105
8.12.2. MonoMux ConLst ...........................................................................................................106
8.12.3. MonoMux ConLstEntry0 ................................................................................................106
8.12.4. MonoMux ConSelectCtrl ................................................................................................107
8.13. MonoMixer Node (NID = 16) ........................................................................................................107
8.13.1. MonoMixer WCap ..........................................................................................................107
8.13.2. MonoMixer ConLst .........................................................................................................109
8.13.3. MonoMixer ConLstEntry0 ..............................................................................................109
8.14. DMic0 Node (NID = 18) ...............................................................................................................110
8.14.1. DMic0 WCap ..................................................................................................................110
8.14.2. DMic0 PinCap ................................................................................................................111
8.14.3. DMic0 PinWCntrl ............................................................................................................112
8.14.4. DMic0 OutAmpCap ........................................................................................................112
8.14.5. DMic0 OutAmpLeft .........................................................................................................113
8.14.6. DMic0 OutAmpRight ......................................................................................................113
8.14.7. DMic0 ConfigDefault ......................................................................................................114
8.15. DMic1 Node (NID = 19) ...............................................................................................................115
8.15.1. DMic1 WCap ..................................................................................................................115
8.15.2. DMic1 PinCap ................................................................................................................116
8.15.3. DMic1 PinWCntrl ............................................................................................................117
8.15.4. DMic1 OutAmpCap ........................................................................................................118
8.15.5. DMic1 OutAmpLeft .........................................................................................................119
8.15.6. DMic1 OutAmpRight ......................................................................................................119
8.15.7. DMic1 ConfigDefault ......................................................................................................119
8.16. InPort0Mux Node (NID = 1A) .......................................................................................................121
IDT™ CONFIDENTIAL AND PROPRIETARY
4-CHANNEL HD AUDIO CODECS OPTIMIZED FOR LOW POWER
5
92HD71B5
V 0.9 09/07
5 Page 
92HD71B5
4-CHANNEL HD AUDIO CODECS OPTIMIZED FOR LOW POWER
PC AUDIO
1.4. Detailed Description
1.4.1.
Low-voltage High Definition Audio Link Signaling
The 92HD71B5 is compatible with either 1.5 V or 3.3 V High Definition Audio Link signaling; the volt-
age selection is performed dynamically based on the input voltage of DVDD_IO. Note that DVDD_IO
is not a logic configuration pin but provides the digital power supply to be used for the High Definition
Audio Link signals.
When in 1.5 V mode, the 92HD71B5 can correctly decode BITCLK, SYNC, RESET# and SDO
because they operate at 1.5 V. Additionally, it will drive SDI_CODEC at 1.5 V. None of the GPIOs are
affected, as they always function at their nominal voltage (DVDD or AVDD).
1.4.2.
Port Functionality
Single function (Input only / output only) ports allow for the highest possible performance.
• Port A supports
• Headphone Out
• Line Out
• Port D supports
• Line Out
• Ports B and C support
• Line In
• Mic with 0/10/20/30/40 dB Mic boost4
• Mono Output cannot be reconfigured
Note4: 40dB boost requires using the IDT driver. When the 40dB mic boost feature is enabled, addi-
tional gain increases greater than 6dB may result in significant audio quality degradation of the
microphone audio input. In particular, when the 40dB MIC boost is active, the SNR, THD+N and DC
offset will significantly degrade regardless of the input signal level.
1.4.3.
Port Characteristics
Ports are designed to be dedicated inputs or outputs only. Universal (Bi-directional) jacks are not
supported. Port A is designed to drive a set of 32 ohm (nominal) headphones or a 10K (nominal)
load with on board shunt resistance as low as 20K ohms (typical - used to maintain coupling CAP
bias.) Line Level outputs are intended to drive an external 10K speaker load (nominal) and an on
board shunt resistor of 20-47K (nominal). However, applications may support load impedances of 5K
ohms and above. Input ports are 47K impedance (nominal) at the pin.
DAC full scale outputs and intended full scale input levels are 1V rms. Line output ports and Head-on
output ports on the 92HD71B5 may be configured for +3dBV full scale output levels by using a ven-
dor specific verb.
Output ports are always on to prevent pops/clicks associated with charging and discharging output
coupling capacitors. This maintains proper bias on output coupling caps even in D3 as long as AVDD
is available. Unused ports should be left unconnected. When updating existing designs to use
92HD71B5, ensure that there are no conflicts between the output ports on 92HD71B5 and existing
circuitry.
IDT™ CONFIDENTIAL AND PROPRIETARY
4-CHANNEL HD AUDIO CODECS OPTIMIZED FOR LOW POWER
11
92HD71B5
V 0.9 09/07
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet 92HD71B5.PDF ] | |
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