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HD49801FB PDF даташит

Спецификация HD49801FB изготовлена ​​​​«ETC» и имеет функцию, называемую «Digital Signal Processing IC».

Детали детали

Номер произв HD49801FB
Описание Digital Signal Processing IC
Производители ETC
логотип ETC логотип 

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HD49801FB Даташит, Описание, Даташиты
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HD49801FB
Digital Signal Processing IC for CCD Cameras
Preliminary
Description
The HD49801FB is an IC that integrates all the
functions required for CCD camera signal
processing (except the CDS and AGC blocks) in a
single chip.
Features
• Generates high quality chroma and luminance
signals using three-line matrix processing
supported by a built-in line memory (1H × 2).
• Allows microprocessor control (over a serial
interface) of all image quality controls.
• Handles all formats; NTSC, PAL, SECAM
(however, does not include a SECAM
encoder).
• Handles 510H/760H CCD image sensors.
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HD49801FB Даташит, Описание, Даташиты
HD49801FB
HD49801FB
Pin Functions
Pin Pin
No. Name
1 PLLPO
2 PLLNO
3 VRI
Signal
PLL posi out
PLL nega out
Vertical reset in
I/O
O
O
I
4 CBLKO Composite blanking out O
5 CSYNCO Composite SYNC out O
6 VDO
7 FVO
8 BFO
9 IDO
Vertical driving out
Field vertical out
Burst flag out
Line ID out
O
O
O
O
10 SSG VSS VSS for SSG
11 FF SCO 4fsc out
12 PAD VSS VSS for PAD
13 X4FSCI 4fsc osc in
14 X4FSCO 4fsc osc out
15 SCO
16 CCK
Sub carrier out
C clock for DAC
17 CO (8)
18 CO (7)
19 CO (6)
20 CO (5)
21 CO (4)
22 CO (3)
23 CO (2)
24 CO (1)
25 TEST1
26 YCK
Chroma out (8): MSB
Chroma out (7)
Chroma out (6)
Chroma out (5)
Chroma out (4)
Chroma out (3)
Chroma out (2)
Chroma out (1): LSB
Test 1
Y clock for DAC
27 YO (8)
28 YO (7)
29 YO (6)
30 YO (5)
31 YO (4)
32 YO (3)
33 YO (2)
34 YO (1)
Y out (8): MSB
Y out (7)
Y out (6)
Y out (5)
Y out (4)
Y out (3)
Y out (2)
Y out (1): LSB
VSS
O
VSS
osc
osc
O
O
O
O
O
O
O
O
O
O
I
O
O
O
O
O
O
O
O
O
Function Description
In PAL/SECAM modes, the fsc and fH gen lock phase
detection output
External reset input for the vertical synchronization
signal; high = reset
Composite horizontal and vertical blanking signal
Composite horizontal and vertical synchronization and
blanking signal
Vertical synchronization signal
Field vertical synchronization signal
Burst flag output
Line ID
PAL: High = (R-Y) +, low = (R-Y) –
SECAM: High = B-Y, low = R-Y
SSG (SYNC signal generator) ground
4fsc output
PAD VSS
4fsc oscillator circuit input
(NTSC: 4fsc = 14.31818 MHz)
4fsc oscillator circuit output
(PAL/SECAM: 4fsc = 17.734475 MHz)
fsc output
Clock output for chroma signal (C) D/A converter;
frequency = 4fsc
Chroma signal (C) output
(Data format: offset binary)
Test pin: Fix at the low level
Clock output for luminance signal (Y) D/A converter;
frequency = 4fsc
Luminance signal (Y) output
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HD49801FB Даташит, Описание, Даташиты
HD49801FB
HD49801FB
Pin Functions (cont)
Pin Pin
No. Name
Signal
35 YPO (8) Y pararell out (8): MSB
36 YPO (7) Y pararell out (7)
37 YPO (6) Y pararell out (6)
38 CORE VDD VDD for core
I/O
O
O
O
VDD
39 YPO (5) Y pararell out (5)
O
40 YPO (4) Y pararell out (4)
O
41 YPO (3) Y pararell out (3)
O
42 YPO (2) Y pararell out (2)
O
43 YPO (1) Y pararell out (1): LSB O
44 YPI (8) Y pararell in (8): MSB I
45 YPI (7) Y pararell in (7)
I
46 YPI (6) Y pararell in (6)
I
47 YPI (5) Y pararell in (5)
I
48 YPI (4) Y pararell in (4)
I
49 YPI (3) Y pararell in (3)
I
50 YPI (2) Y pararell in (2)
I
51 YPI (1) Y pararell in (1): LSB I
52 CPO (4) C pararell out (4): MSB O
53 CPO (3) C pararell out (3)
O
54 CPO (2) C pararell out (2)
O
55 CPO (1) C pararell out (1): LSB O
56 CPI (4) C pararell in (4): MSB I
57 CPI (3) C pararell in (3)
I
58 CPI (2) C pararell in (2)
I
59 CPI (1) C pararell in (1): LSB I
60 NRYBYO R-Y, B-Y phase out
O
61 DICKO Digital interface clock out O
62 CORE VSS VSS for core
VSS
63 HREFI Horizontal reference in I
64 HGI
65 SCKI
66 ADI (9)
67 ADI (8)
68 ADI (7)
Horizontal gate in
Sensor clock in
AD in (9): MSB
AD in (8)
AD in (7)
I
I
I
I
I
Function Description
Y digital interface output
Outputs the post-gamma compensation Y signal
VDD
for
core,
VDD
=
5
V
+0.25
–0.50
V
V
Y digital interface output
Y digital interface input
C digital interface output (data format: two’s
complement)
Color difference signals R-Y and B-Y
Upper to lower order
C digital interface input (data format: two’s
complement)
C digital interface phase output; high = (B-Y) phase,
low = (R-Y) phase
Digital interface clock output, frequency = fs
VSS for core
Horizontal scan reference signal
Reference for memory start/stop, BF, CBLK, and
CSYNC
Line signals (two types) determination input; high = a,
b; low = c, d (state data A7)
Sensor clock (system clock) fs input
A/D input
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