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PDF HD49330AHF Data sheet ( Hoja de datos )
| Número de pieza | HD49330AHF | |
| Descripción | CDS/PGA & 12-bit A/D Converter | |
| Fabricantes | Renesas Technology | |
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HD49330AF/AHF
CDS/PGA & 12-bit A/D Converter
REJ03F0102-0100Z
(Previous: ADE-207-344)
Rev.1.0
Apr.05.2004
Description
The HD49330AF/AHF is a CMOS IC that provides CDS-PGA analog processing (CDS/PGA) suitable for CCD camera
digital signal processing systems together with a 12-bit A/D converter in a single chip.
Functions
• Correlated double sampling
• PGA
• Offset compensation
• Serial interface control
• 12-bit ADC
• Operates using only the 3 V voltage
• Corresponds to switching mode of power dissipation and operating frequency
Power dissipation: 150 mW (Typ), maximum frequency: 36 MHz
Power dissipation: 80 mW (Typ), maximum frequency: 20 MHz
• ADC direct input mode
• Y-IN direct input mode
• QFP 48-pin package
Features
• Suppresses low-frequency noise output from CCD by the S/H type correlated double sampling.
• The S/H response frequency characteristics for the reference level can be adjusted using values of external parts and
registers.
• High sensitivity is achieved due to the high S/N ratio and a wide coverage provided by a PG amplifier.
• Feedback is used to compensate and reduce the DC offsets including the output DC offset due to PGA gain change
and the CCD offset in the CDS (correlated double sampling) amplifier input.
• PGA, standby mode, etc., is achieved via a serial interface.
• High precision is provided by a 12-bit-resolution A/D converter.
Rev.1.0, Apr.05.2004, page 1 of 19
1 page  
HD49330AF/AHF
Block Diagram
ADCIN 27
Y IN 26
PBLK 26
CDSIN 26
BLKSH 28
BLKC 28
CDS
16 18 19
Timing
generator
31 16 18 19 19
PGA
12 bit
ADC
BLKFB 29
DC offset
compensation
circuit
Serial
interface
Bias
generator
17
44 45 43
35 32 34 33
42 OEB
11 D11
10 D10
9 D9
8 D8
7 D7
6 D6
5 D5
4 D4
3 D3
2 D2
D1
D0
Rev.1.0, Apr.05.2004, page 5 of 19
5 Page 
HD49330AF/AHF
Detailed Timing Specifications
Detailed Timing Specifications when CDSIN Input Mode is Used
Figure 3 shows the detailed timing specifications when the CDSIN input mode is used, and table 8 shows each timing
specification.
CDSIN
SPBLK
SPSIG
ADCLK
D0 to D11
Black Signal
level level
(2) (1)
(3)
(5)
(4)
(6)
(7) (8)
(9)
(10)
Vth
Vth
Vth
Note: 1. When serial data Spinv bit is set to low. (When the Spinv bit is set to high, the polarities
of the SPBLK and the SPSIG are inverted.)
Figure 3 Detailed Timing Chart when CDSIN Input Mode is Used
Table 8 Timing Specifications when the CDSIN Input Mode is Used
No. Timing
Symbol Min
(1)
(2)
(3)
(4)
(5)
(6)
(7), (8)
Black-level signal fetch time
SPBLK low period *1
Signal-level fetch time
SPSIG low period *1
SPBLK rising to SPSIG rising time *1
SPSIG rising to ADCLK rising inhibition time *1
ADCLK tWH min./tWL min.
tCDS1
tCDS2
tCDS3
tCDS4
tCDS5
tCDS6
tCDS7, 8
—
Typ × 0.8
—
Typ × 0.8
Typ × 0.85
1
11
(9) ADCLK rising to digital output hold time
(10) ADCLK rising to digital output delay time
tCHLD9
tCOD10
3
—
Note: 1. SPBLK and SPSIG polarities when serial data Spinv bit is set to low.
Typ
(1.5)
1/4fCLK
(1.5)
1/4fCLK
1/2fCLK
5
—
7
16
Max
—
Typ × 1.2
—
Typ × 1.2
Typ × 1.15
9
—
—
24
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
OBP Detailed Timing Specifications
Figure 4 shows the OBP detailed timing specifications.
The OB period is from the fifth to the twelfth clock cycle after the OB pulse is input. The average of the black signal
level is taken for eight input cycles during the OB period and becomes the clamp level (DC standard).
OB period *1
CDSIN
N N+1
N+5
N+12
N+13
OBP
OB pulse > 2 clock cycles This edge is used, when OBP pulse-width period is clamp-on.
When serial data OBPinv bit is set to low
(When the OBPinv is set to high, the polarity of the OBP is inverted.)
Note: 1. Shifts ±1 clock cycle depending on the OBP input timing.
Figure 4 OBP Detailed Timing Specifications
Rev.1.0, Apr.05.2004, page 11 of 19
11 Page | ||
| Páginas | Total 20 Páginas | |
| PDF Descargar | [ Datasheet HD49330AHF.PDF ] | |
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