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PDF WM8501 Data sheet ( Hoja de datos )
| Número de pieza | WM8501 | |
| Descripción | 24-bit 192kHz Stereo DAC | |
| Fabricantes | Wolfson Microelectronics | |
| Logotipo |  |
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WM8501
24-bit 192kHz Stereo DAC with 1.7Vrms Line Driver
DESCRIPTION
The WM8501 is a high performance stereo DAC with an
integrated 1.7Vrms line driver. It is designed for audio
applications that require a high voltage output along with
enhanced load drive capability.
The WM8501 supports data input word lengths from 16 to
24-bits and sampling rates up to 192kHz. The WM8501
consists of a serial interface port, digital interpolation filters,
multi-bit sigma delta modulators and stereo DAC in a 14-
lead SOIC package.
The hardware control interface is used for the selection of
audio data interface format, enable and de-emphasis. The
WM8501 supports I2S, right Justified or DSP interfaces.
Operating on separate analog and digital supplies the
WM8501 offers very lower power consumption from the
digital section, whilst supporting enhanced load drive from
the analogue output.
FEATURES
Stereo DAC with 1.7Vrms line driver from 5V analogue
supply
Audio performance
- 100dB SNR (‘A’ weighted @ 48kHz)
- -88dB THD
DAC Sampling Frequency: 8kHz – 192kHz
Pin Selectable Audio Data Interface Format
- I2S, 16-bit Right Justified or DSP
14-lead SOIC package
4.5V - 5.5V analogue, 2.7V - 5.5V digital supply operation
APPLICATIONS
STB
DVD
Digital TV
BLOCK DIAGRAM
WOLFSON MICROELECTRONICS plc
Production Data, February 2013, Rev 4.3
Copyright 2013 Wolfson Microelectronics plc
1 page  
Production Data
WM8501
ABSOLUTE MAXIMUM RATINGS
Absolute Maximum Ratings are stress ratings only. Permanent damage to the device may be caused by continuously operating at
or beyond these limits. Device functional operating limits and guaranteed performance specifications are given under Electrical
Characteristics at the test conditions specified.
ESD Sensitive Device. This device is manufactured on a CMOS process. It is therefore generically susceptible
to damage from excessive static voltages. Proper ESD precautions must be taken during handling and storage
of this device.
Wolfson tests its package types according to IPC/JEDEC J-STD-020 for Moisture Sensitivity to determine acceptable storage
conditions prior to surface mount assembly. These levels are:
MSL1 = unlimited floor life at <30C / 85% Relative Humidity. Not normally stored in moisture barrier bag.
MSL2 = out of bag storage for 1 year at <30C / 60% Relative Humidity. Supplied in moisture barrier bag.
MSL3 = out of bag storage for 168 hours at <30C / 60% Relative Humidity. Supplied in moisture barrier bag.
The Moisture Sensitivity Level for each package type is specified in Ordering Information.
CONDITION
Analogue supply voltage
Digital supply voltage
Voltage range digital inputs
Master clock frequency
Operating temperature range, TA
Storage temperature prior to soldering
Storage temperature after soldering
MIN MAX
-0.3V
+7V
-0.3V
+7V
DGND -0.3V
DVDD +0.3V
38.462MHz
-40C
+85C
30C max / 85% RH max
-65C
+150C
RECOMMENDED OPERATING CONDITIONS
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP MAX
Digital supply range
DVDD
2.7 5.5
Analogue supply range
AVDD
4.5 5.5
Ground
AGND, DGND
0
Difference DGND to AGND
-0.3 0 +0.3
Note: Digital supply DVDD must never be more than 0.3V greater than AVDD for normal operation of the device.
UNIT
V
V
V
V
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PD, Rev 4.3, February 2013
5
5 Page 
Production Data
WM8501
RIGHT JUSTIFIED MODE
The WM8501 supports word lengths of 16-bits in right justified mode.
In right justified mode, the digital audio interface receives data on the DIN input. Audio Data is time
multiplexed with LRCLK indicating whether the left or right channel is present. LRCLK is also used
as a timing reference to indicate the beginning or end of the data words.
In right justified mode, the minimum number of BCLKs per LRCLK period is 2 times the selected
word length. LRCLK must be high for a minimum of word length BCLKs and low for a minimum of
word length BCLKs. Any mark to space ratio on LRCLK is acceptable provided the above
requirements are met.
In right justified mode, the LSB is sampled on the rising edge of BCLK preceding a LRCLK
transition. LRCLK is high during the left samples and low during the right samples.
Figure 4 Right Justified Mode Timing Diagram
DSP MODE
A DSP compatible, time division multiplexed format is also supported by the WM8501. This format
is of the type where a ‘synch’ pulse is followed by two data words (left and right) of predetermined
word length. (16-bits). The ‘synch’ pulse replaces the normal duration LRCLK, and DSP mode is
auto-detected by the shorter than normal duration of the LRCLK. If LRCLK is of 4 BCLK or less
duration, the DSP compatible format is selected. Mode A and Mode B clock formats are
supported, selected by the state of the FORMAT pin.
LRCLK
BCLK
DIN
1
max 4 BCLK's
1/f
LEFT CHANNEL
RIGHT CHANNEL
12
MSB
11
1
LSB
2
Input Word Length (16 bits)
11
1
NO VALID DATA
Figure 5 DSP Mode A Timing
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PD, Rev 4.3, February 2013
11
11 Page | ||
| Páginas | Total 21 Páginas | |
| PDF Descargar | [ Datasheet WM8501.PDF ] | |
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