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PDF WBLXT9785E Data sheet ( Hoja de datos )

Número de pieza WBLXT9785E
Descripción Advanced 8-Port 10/100 Mbps PHY Transceivers
Fabricantes intel　
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Intel® LXT9785 and Intel® LXT9785E
Advanced 8-Port 10/100 Mbps PHY
Transceivers
Datasheet
The Intel® LXT9785 and Intel® LXT9785E are 8-port Fast Ethernet PHY Transceivers
supporting IEEE 802.3 physical layer applications at 10 Mbps and 100 Mbps. These devices
provide Serial/Source Synchronous Serial Media Independent Interfaces (SMII/SS-SMII) and
Reduced Media Independent Interface (RMII) for switching and other independent port
applications. The LXT9785 and LXT9785E are identical except for the IP telephony features
included in the LXT9785E transceiver. The LXT9785E is an enhanced version of the LXT9785
that detects Data Terminal Equipment (DTE) requiring power from the switch over a CAT5
cable. The system uses the information collected by the LXT97985E to apply power if the DTE
at the far end requires power over the cable, such as an IP telephone.
Each network port can provide a twisted-pair (TP) or Low-Voltage Positive Emitter Coupled
Logic (LVPECL) interface. The twisted-pair interface supports 10 Mbps and 100 Mbps
(10BASE-T and 100BASE-TX) Ethernet over twisted-pair. The LVPECL interface supports
100 Mbps (100BASE-FX) Ethernet over fiber-optic media.
The LXT9785/LXT9785E provides three discrete LED driver outputs for each port. The devices
support both half-duplex and full-duplex operation at 10 Mbps and 100 Mbps and require only a
single 2.5 V power supply.
Applications
„ Enterprise switches
„ IP telephony switches
Product Features
„ Storage Area Networks
„ Multi-port Network Interface Cards (NICs)
„ Eight IEEE 802.3-compliant 10BASE-T or
100BASE-TX ports with integrated filters.
„ 100BASE-FX fiber-optic capability on all
ports.
„ 2.5 V operation.
„ Low power consumption; 250 mW per port
typical.
„ Multiple RMII or SMII/SS-SMII ports for
independent PHY port operation.
„ Auto MDI/MDIX crossover capability.
„ Proprietary Optimal Signal Processing™
architecture improves SNR by 3 dB over
ideal analog filters.
„ Optimized for dual-high stacked RJ-45
applications.
„ MDIO sectionalization into 2x4 or 1x8
configurations.
„ Supports both auto-negotiation systems and
legacy systems without auto-negotiation
capability.
„ Robust baseline wander correction.
„ Configurable through the MDIO port or
external control pins.
„ JTAG boundary scan.
„ 208-pin PQFP: LXT9785HC,
LXT9785EHC, LXT9785HE.
„ 241-ball BGA: LXT9785BC,
LXT9785EBC.
„ 196-ball BGA: LXT9785MBC
„ DTE detection for remote powering
applications (LXT9785E only).
„ Extended temperature operation of -40oC to
+85oC (LXT9785HE).
Document Number: 249241
Revision Number: 007
Revision Date: August 28, 2003

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Contents
4.10
4.11
4.12
4.13
4.14
4.9.1 100BASE-X Network Operations .........................................................................145
4.9.2 100BASE-X Protocol Sublayer Operations..........................................................145
4.9.2.1 PCS Sublayer ......................................................................................145
4.9.3 PMA Sublayer ......................................................................................................147
4.9.3.1 Link ......................................................................................................148
4.9.3.2 Link Failure Override............................................................................148
4.9.3.3 Carrier Sense/Data Valid (RMII) ..........................................................148
4.9.3.4 Carrier Sense (SMII) ............................................................................148
4.9.3.5 Receive Data Valid (SMII)....................................................................148
4.9.3.6 Twisted-Pair PMD Sublayer .................................................................149
4.9.3.7 Fiber PMD Sublayer.............................................................................149
10 Mbps Operation ...........................................................................................................150
4.10.1 Preamble Handling ..............................................................................................150
4.10.2 Dribble Bits ..........................................................................................................151
4.10.3 Link Test ..............................................................................................................151
4.10.3.1 Link Failure ..........................................................................................151
4.10.4 Jabber ..................................................................................................................151
DTE Discovery Process ....................................................................................................152
4.11.1 Definitions ............................................................................................................152
4.11.2 Interaction between Processor, MAC, and PHY ..................................................153
4.11.3 Management Interface and Control .....................................................................153
4.11.4 DTE Discovery Process Flow ..............................................................................154
4.11.5 DTE Discovery Behavior......................................................................................155
Monitoring Operations ......................................................................................................157
4.12.1 Monitoring Auto-Negotiation ................................................................................157
4.12.2 Per-Port LED Driver Functions ............................................................................157
4.12.3 Out-of-Band Signaling .........................................................................................158
4.12.4 Boundary Scan Interface .....................................................................................159
4.12.5 State Machine ......................................................................................................159
4.12.6 Instruction Register ..............................................................................................159
4.12.7 Boundary Scan Register ......................................................................................159
Cable Diagnostics Overview .............................................................................................160
4.13.1 Features...............................................................................................................160
4.13.2 Operation .............................................................................................................160
4.13.2.1 Short and Long Cable Testing Requirements ......................................160
4.13.2.2 Precision ..............................................................................................160
4.13.3 Implementation Considerations ...........................................................................161
4.13.4 Basic Implementation ..........................................................................................161
Link Hold-Off Overview .....................................................................................................162
4.14.1 Features...............................................................................................................162
4.14.2 Operation .............................................................................................................163
5.0 Application Information ............................................................................................................164
5.1 Design Recommendations................................................................................................164
5.2 General Design Guidelines ...............................................................................................164
5.2.1 Power Supply Filtering .........................................................................................164
5.2.2 Power and Ground Plane Layout Considerations................................................165
5.2.2.1 Chassis Ground ...................................................................................165
5.2.3 MII Terminations ..................................................................................................165
5.2.4 Twisted-Pair Interface ..........................................................................................165
5.2.4.1 Magnetic Requirements .......................................................................166
Datasheet
Document Number: 249241
Revision Number: 007
Revision Date: August 28, 2003
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Contents
Revision Number: 007
Revision Date: August 28, 2003
Page
120
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161
Description
Modified/added text under Section 4.3.2, “Internal Loopback”.
Modified text under Section 4.3.6, “MII Isolate”.
Section 4.3.7, “MDIO Management Interface”:
Added note under second paragraph.
Added last paragraph.
Added note under Section 4.3.8, “MII Sectionalization”.
Added new Section 4.3.11, “FIFO Initial Fill Values”
Modified paragraph three under Section 4.4.1, “Power Requirements”.
Added notes under second and last paragraphs under Section 4.5.3, “Power-Down Mode”.
Modified last bullet under Section 4.5.3.1, “Global (Hardware) Power Down”.
Added last paragraph to Section 4.5.4, “Reset”.
Modified Table 42 “Intel® LXT9785/9785E Global Hardware Configuration Settings”.
Change heading and modified last line under Section 4.6.1.2, “Manual Next Page Exchange”.
Section 4.6.1.4, “Link Criteria”:
Changed scrambler to descrambler in first line.
Modified second paragraph.
Added two new paragraphs.
Added second paragraph under Section 4.6.1.5, “Parallel Detection”.
Modified paragraphs under Section 4.6.1.6, “Reliable Link Establishment While Auto MDI/MDIX is
Enabled in Forced Speed Mode”.
Changed “1110” to “0101” under Section 4.7.4.3, “Receive Error”.
Added note under first paragraph of Section 4.8, “RMII Operation”
Changed “asynchronously” to “synchronously” in second paragraph under Section 4.9.3.3, “Carrier
Sense/Data Valid (RMII)”.
Modified last sentence in first paragraph under Section 4.9.3.4, “Carrier Sense (SMII)”.
Modified paragraph under Section 4.9.3.6.3, “Polarity Correction”.
Added note under Section 4.9.3.7, “Fiber PMD Sublayer”.
Added second paragraph under Section 4.9.3.7.1, “Far End Fault Indications”.
Modified/added text under Section 4.10.1, “Preamble Handling”.
Modified text under Section 4.10.4, “Jabber”.
Modified first paragraph under Section 4.11, “DTE Discovery Process”.
Modified Item 1 of Section 4.11.2, “Interaction between Processor, MAC, and PHY”.
Modified second paragraph under Section 4.11.4, “DTE Discovery Process Flow”.
Added Section 4.11.5, “DTE Discovery Behavior”
Added BGA15 information into first paragraph under Section 4.12.2, “Per-Port LED Driver
Functions”.
Added last sentence to first paragraph and note under first paragraph under Section 4.12.3, “Out-of-
Band Signaling”.
Added Section 4.13, “Cable Diagnostics Overview”.
Modified/added text under Section 4.13.3, “Implementation Considerations”.
Datasheet
Document Number: 249241
Revision Number: 007
Revision Date: August 28, 2003
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