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PDF S-93C56B Data sheet ( Hoja de datos )
| Número de pieza | S-93C56B | |
| Descripción | (S-93Cx6B) CMOS SERIAL E2PROM | |
| Fabricantes | Seiko Instruments | |
| Logotipo |  |
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S-93C46B/56B/66B H Series
www.sii-ic.com
© Seiko Instruments Inc., 2010-2015
FOR AUTOMOTIVE 105°C OPERATION
3-WIRE SERIAL E2PROM
Rev.2.1_00
The S-93C46B/56B/66B H Series is a high temperature operation 3-wire serial E2PROM for automotive components. The
S-93C46B/56B/66B H Series has the capacity of 1 K-bit, 2 K-bit and 4 K-bit, and the organization is 64-word × 16-bit, 128-
word × 16-bit and 256-word × 16-bit. It is capable of sequential read, at which time addresses are automatically incremented
in 16-bit blocks.
The communication method is by the Microwire bus.
Features
• Operating voltage range:
Read
2.7 V to 5.5 V (Ta = −40°C to +105°C)
Write
2.7 V to 5.5 V (Ta = −40°C to +105°C)
• Operation frequency:
• Write time:
1.0 MHz (VCC = 4.5 V to 5.5 V, Ta = −40°C to +105°C)
8.0 ms max.
• Sequential read capable
• Write protect function during the low power supply voltage
• Function to protect against write due to erroneous instruction recognition
• Endurance:
106 cycles/word*1 (Ta = +85°C)
5 × 105 cycles/word*1 (Ta = +105°C)
• Data retention:
100 years (Ta = +25°C)
20 years (Ta = +105°C)
• Memory capacity:
S-93C46B 1 K-bit
S-93C56B 2 K-bit
S-93C66B 4 K-bit
• Initial delivery state:
FFFFh
• Operation temperature range: Ta = −40°C to +105°C
• Lead-free (Sn 100%), halogen-free*2
• AEC-Q100 qualified*3
*1. For each address (Word: 16-bit)
*2. Refer to “ Product Name Structure” for details.
*3. Contact our sales office for details.
Packages
• 8-Pin SOP (JEDEC)
• 8-Pin TSSOP
• TMSOP-8
Caution Before using the product in medical equipment or automobile equipment including car audio, keyless
entry and engine control unit, contact to SII is indispensable.
Seiko Instruments Inc.
1
1 page  
Rev.2.1_00
FOR AUTOMOTIVE 105°C OPERATION 3-WIRE SERIAL E2PROM
S-93C46B/56B/66B H Series
AEC-Q100 Qualified
This IC supports AEC-Q100 for operation temperature grade 2.
Contact our sales office for details of AEC-Q100 reliability specification.
Instruction Sets
1. S-93C46B
Table 4
Instruction
Start Bit
Operation
Code
Address
Data
SK input clock
1 23456789
10 to 25
READ (Read data)
1 1 0 A5 A4 A3 A2 A1 A0 D15 to D0 Output*1
WRITE (Write data)
1 0 1 A5 A4 A3 A2 A1 A0 D15 to D0 Input
ERASE (Erase data)
1 1 1 A5 A4 A3 A2 A1 A0
⎯
WRAL (Write all)
1 0 0 0 1 x x x x D15 to D0 Input
ERAL (Erase all)
1 0010xxxx
⎯
EWEN (Write enable)
1 0011xxxx
⎯
EWDS (Write disable)
1 0000xxxx
⎯
*1. When the 16-bit data in the specified address has been output, the data in the next address is output.
Remark x: Don’t care
2. S-93C56B
Table 5
Instruction
Start Bit
Operation
Code
Address
Data
SK input clock
1 2 3 4 5 6 7 8 9 10 11
12 to 27
READ (Read data)
1 1 0 x A6 A5 A4 A3 A2 A1 A0 D15 to D0 Output*1
WRITE (Write data)
1 0 1 x A6 A5 A4 A3 A2 A1 A0 D15 to D0 Input
ERASE (Erase data)
1 1 1 x A6 A5 A4 A3 A2 A1 A0
⎯
WRAL (Write all)
1 0 0 0 1 x x x x x x D15 to D0 Input
ERAL (Erase all)
1 0 0 10xxxxxx
⎯
EWEN (Write enable)
1 0 0 11xxxxxx
⎯
EWDS (Write disable)
1 0 0 00xxxxxx
⎯
*1. When the 16-bit data in the specified address has been output, the data in the next address is output.
Remark x: Don’t care
3. S-93C66B
Table 6
Instruction
Start Bit
Operation
Code
Address
Data
SK input clock
1 2 3 4 5 6 7 8 9 10 11
12 to 27
READ (Read data)
1 1 0 A7 A6 A5 A4 A3 A2 A1 A0 D15 to D0 Output*1
WRITE (Write data)
1 0 1 A7 A6 A5 A4 A3 A2 A1 A0 D15 to D0 Input
ERASE (Erase data)
1 1 1 A7 A6 A5 A4 A3 A2 A1 A0
⎯
WRAL (Write all)
1 0 0 0 1 x x x x x x D15 to D0 Input
ERAL (Erase all)
1 0 0 10xxxxxx
⎯
EWEN (Write enable)
1 0 0 11xxxxxx
⎯
EWDS (Write disable)
1 0 0 00xxxxxx
⎯
*1. When the 16-bit data in the specified address has been output, the data in the next address is output.
Remark x: Don’t care
Seiko Instruments Inc.
5
5 Page 
Rev.2.1_00
FOR AUTOMOTIVE 105°C OPERATION 3-WIRE SERIAL E2PROM
S-93C46B/56B/66B H Series
Operation
All instructions are executed by inputting DI in synchronization with the rising edge of SK after CS goes high. An
instruction set is input in the order of start bit, instruction, address, and data.
Instruction input finishes when CS goes low. A low level must be input to CS between commands during tCDS. While a
low level is being input to CS, the S-93C46B/56B/66B is in standby mode, so the SK and DI inputs are invalid and no
instructions are allowed.
Start Bit
A start bit is recognized when the DI pin goes high at the rise of SK after CS goes high. After CS goes high, a start bit
is not recognized even if the SK pulse is input as long as the DI pin is low.
1. Dummy clock
SK clocks input while the DI pin is low before a start bit is input are called dummy clocks. Dummy clocks are
effective when aligning the number of instruction sets (clocks) sent by the CPU with those required for serial
memory operation. For example, when a CPU instruction set is 16 bits, the number of instruction set clocks can be
adjusted by inserting a 7-bit dummy clock for the S-93C46B and a 5-bit dummy clock for the S-93C56B/66B.
2. Start bit input failure
• When the output status of the DO pin is high during the verify period after a write operation, if a high level is input
to the DI pin at the rising edge of SK, the S-93C46B/56B/66B recognizes that a start bit has been input. To
prevent this failure, input a low level to the DI pin during the verify operation period (refer to “4.1 Verify
operation”).
• When a 3-wire interface is configured by connecting the DI input pin and DO output pin, a period in which the
data output from the CPU and the serial memory collide may be generated, preventing successful input of the
start bit. Take the measures described in “ 3-Wire Interface (Direct Connection between DI and DO)”.
Seiko Instruments Inc.
11
11 Page | ||
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| PDF Descargar | [ Datasheet S-93C56B.PDF ] | |
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