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PDF N16T1618C2A Data sheet ( Hoja de datos )
| Número de pieza | N16T1618C2A | |
| Descripción | 16M Yltra Low Power CMOS PSRAM | |
| Fabricantes | NanoAmp Solutions | |
| Logotipo |  |
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www.DataSheet4U.com
NanoAmp Solutions, Inc.
1982 Zanker Road, San Jose, CA 95112
ph: 408-573-8878, FAX: 408-573-8877
www.nanoamp.com
N16T1618C2(D1/A1)A
Advance Information
16Mb Ultra-Low Power Asynchronous CMOS PSRAM
1M x 16 bit
Overview
Features
The N16T1618C2(D1/A1)A is an integrated
memory device containing a 16 Mbit Pseudo Static
Random Access Memory using a self-refresh
DRAM array organized as 1,048,576 words by 16
bits. It is designed to be compatible in operation
and interface to standard 6T SRAMS. The device
is designed for low standby and operating current
and includes a power-down feature to
automatically enter standby mode. The device is
available in a 2 CE (chip enable) version and two
ZZ (deep sleep) versions. The ZZ version includes
several power saving modes: a deep sleep mode
where data is not retained in the array and partial
array refresh mode where data is retained in a
portion of the array. Both these modes reduce
standby current drain. The VFBGA package has
separate power rails, VccQ and VssQ for the I/O to
be run from a separate power supply from the
device core.
Product Family
• Dual voltage for Optimum Performance
VCCQ and VSSQ for separate I/O power rails
Vcc - 1.65V to 2.2 V
Vccq - 1.65V to 3.6V
• Fast Cycle Times
TACC < 85 nS
• Very low standby current
ISB < 40µA @ 1.8V
• Very low operating current
Icc < 25mA
• Memory expansion with CE and OE
• Automatic power down mode
• 48-Pin VFBGA, Wafers Available
Part Number
Feature
Package Operating
Power
Type Temperature Supply
Speed
Standby Operating
Current (ISB), Current
Max (Icc), Max
N16T1618C2AZ
N16T1618D1AZ
N16T1618A1AZ
2 CE
Deep Sleep Disabled 48 - BGA
Deep Sleep Active
Pin Configuration
123456
A LB OE
A0
A1
A2
CE2/
ZZ
B I/O8 UB A3 A4 CE1 I/O0
C I/O9 I/O10 A5 A6 I/O1 I/O2
D VSSQ I/O11 A17 A7 I/O3 VCC
E VCCQ I/O12 DNU A16 I/O4 VSS
F I/O14 I/O13 A14 A15 I/O5 I/O6
G I/O15 A19 A12 A13 WE I/O7
H A18 A8
A9 A10 A11 NC
48 Pin BGA (top)
6 x 8 mm
-30oC to +85oC 1.65V - 2.2V 85ns @ 1.65V 40 µA @ 1.8V 3 mA @ 1MHz
Pin Descriptions
Pin Name
A0-A19
WE
CE1
CE2
ZZ
OE
LB
UB
I/O0-I/O15
VCC
VSS
VCCQ
VSSQ
DNU
Pin Function
Address Inputs
Write Enable Input
Chip Enable Input
Chip Enable Input (only for CE2
device)
Deep Sleep Input (only for A1 or D1
deep sleep device)
Output Enable Input
Lower Byte Enable Input
Upper Byte Enable Input
Data Inputs/Outputs
Power
Ground
Power I/O pin only
Ground I/O pin only
Do Not Use (or connect to VSS)
Stock No. 23183 - 04 4/03
The specifications of this device are subject to change without notice. For latest documentation see http://www.nanoamp.com.
1
1 page  
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NanoAmp Solutions, Inc.
N16T1618C2(D1/A1)A
Advance Information
Timings
Read
Cycle
Write
Cycle
All Cycle
Item
Symbol
Read Cycle Time
Address Access Time
Chip Enable to Valid Output
Output Enable to Valid Output
Byte Select to Valid Output
Chip Enable to Low-Z output
Output Enable to Low-Z Output
Byte Select to Low-Z Output
Chip Disable to High-Z Output
Output Disable to High-Z Output
Byte Select Disable to High-Z Output
Output Hold from Address Change
tRC
tAA
tCO
tOE
tLB, tUB
tLZ
tOLZ
tLBZ, tUBZ
tHZ
tOHZ
tLBHZ, tUBHZ
tOH
Min.
85
10
5
10
0
0
0
5
Max.
85
85
15
85
20
20
20
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Write Cycle Time
Chip Enable to End of Write
Address Valid to End of Write
Byte Select to End of Write
Write Pulse Width
Write Recovery Time
Write to High-Z Output
Address Setup Time
Data to Write Time Overlap
Data Hold from Write Time
End Write to Low-Z Output
tWC
tCW
tAW
tLBW, tUBW
tWP
tWR
tWHZ
tAS
tDW
tDH
tOW
85
85
85
85
65
0
0
25
0
5
30000
20
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Address Skew
tSK 10 ns
Stock No. 23183 - 04 4/03
The specifications of this device are subject to change without notice. For latest documentation see http://www.nanoamp.com.
5
5 Page 
www.DataSheet4U.com
NanoAmp Solutions, Inc.
N16T1618C2(D1/A1)A
Advance Information
VAR Update and Deep Sleep Timings
Item
Symbol
PAR and RMS ZZ low to WE low
Chip (CE, UB/LB) deselect to ZZ low
ZZ low after WE high
Deep Sleep Mode
Deep Sleep Recovery
1) Applies only for setting the register for RMS mode.
tzzwe
tcdzz
tzzh 1
tzzmin
tr
Min
0
20
10
200
Address Patterns for PAR (A3 = 0, A4 = 1)
Max
1000
Unit
ns
ns
ns
us
us
A2 A1 A0
Active Section
Address space
Size Density
0 1 1 One-quarter of die 00000h - 3FFFFh 256Kb x 16 4Mb
0 1 0 One-half of die
00000h - 7FFFFh 512Kb x 16 8Mb
0 0 1 Three-quarters of die 00000h - BFFFFh 768Kb x 16 12Mb
1 1 1 One-quarter of die C0000h - FFFFh 256Kb x 16 4Mb
1 1 0 One-half of die
80000h - FFFFFh 512Kb x 16 8Mb
1 0 1 Three-quarters of die 40000h - FFFFFh 768Kb x 16 12Mb
Address patterns for RMS (A3 = 1, A4 = 1)
A2 A1 A0
Active Section
Address space
A19 A18
Size
Density
0 1 1 One-quarter of die 00000h - 3FFFFh 0 0 256Kb x 16 4Mb
0 1 0 One-half of die
00000h - 7FFFFh 0 x 512Kb x 16 8Mb
0 0 1 Three-quarters of die 00000h - BFFFFh 0 0 768Kb x 16 12Mb
01
10
0 0 0 Full die
00000h - FFFFFh x x 1Mb x 16 16Mb
1 1 1 One-quarter of die C0000h - FFFFh 1 1 256Kb x 16 4Mb
1 1 0 One-half of die
80000h - FFFFFh 1 x 512Kb x 16 8Mb
1 0 1 Three-quarters of die 40000h - FFFFFh 1 1 768Kb x 16 12Mb
10
01
1 0 0 Full die
00000h - FFFFFh x x 1Mb x 16 16Mb
Stock No. 23183 - 04 4/03
The specifications of this device are subject to change without notice. For latest documentation see http://www.nanoamp.com.
11
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| PDF Descargar | [ Datasheet N16T1618C2A.PDF ] | |
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