DataSheet26.com

SCC2681 PDF даташит

Спецификация SCC2681 изготовлена ​​​​«NXP Semiconductors» и имеет функцию, называемую «Dual asynchronous receiver/transmitter».

Детали детали

Номер произв SCC2681
Описание Dual asynchronous receiver/transmitter
Производители NXP Semiconductors
логотип NXP Semiconductors логотип 

29 Pages
scroll

No Preview Available !

SCC2681 Даташит, Описание, Даташиты
INTEGRATED CIRCUITS
SCC2681
Dual asynchronous receiver/transmitter
(DUART)
Product data
2004 Apr 06
Philips
Semiconductors









No Preview Available !

SCC2681 Даташит, Описание, Даташиты
Philips Semiconductors
Dual asynchronous receiver/transmitter (DUART)
Product data
SCC2681
DESCRIPTION
The Philips Semiconductors SCC2681 Dual Universal
Asynchronous Receiver/Transmitter (DUART) is a single-chip
MOS-LSI communications device that provides two independent
full-duplex asynchronous receiver/transmitter channels in a single
package. It interfaces directly with microprocessors and may be
used in a polled or interrupt driven system. It is manufactured in a
CMOS process.
The operating mode and data format of each channel can be
programmed independently. Additionally, each receiver and
transmitter can select its operating speed as one of eighteen fixed
baud rates, a 16× clock derived from a programmable counter/timer,
or an external 1× or 16× clock. The baud rate generator and
counter/timer can operate directly from a crystal or from external
clock inputs. The ability to independently program the operating
speed of the receiver and transmitter make the DUART particularly
attractive for dual-speed channel applications such as clustered
terminal systems.
Each receiver is quadruply buffered to minimize the potential of
receiver over-run or to reduce interrupt overhead in interrupt driven
systems. In addition, a flow control capability is provided to disable a
remote DUART transmitter when the buffer of the receiving device is
full.
Also provided on the SCC2681 are a multipurpose 7-bit input port
and a multipurpose 8-bit output port. These can be used as general
purpose I/O ports or can be assigned specific functions (such as
clock inputs or status/interrupt outputs) under program control.
The SCC2681 is available in three package versions: 40-pin and
28-pin DIPs (both 0.6” wide); and a 44-pin PLCC.
FEATURES
Dual full-duplex asynchronous receiver/transmitter
Quadruple buffered receiver data registers
Programmable data format
5 to 8 data bits plus parity
Odd, even, no parity or force parity
1, 1.5 or 2 stop bits programmable in 1/16-bit increments
Programmable baud rate for each receiver and transmitter
selectable from:
22 fixed rates: 50 to 115.2 k baud
16-bit programmable Counter/Timer
Non-standard rates to 115.2 kb
One user-defined rate derived from programmable
timer/counter
External 1× or 16× clock
Parity, framing, and overrun error detection
False start bit detection
Line break detection and generation
Programmable channel mode
Normal (full-duplex)
Automatic echo
Local loopback
Remote loopback
Multi-function programmable 16-bit counter/timer
Multi-function 7-bit input port
Can serve as clock or control inputs
Change of state detection on four inputs
100 ktypical pull-up resistor
Multi-function 8-bit output port
Individual bit set/reset capability
Outputs can be programmed to be status/interrupt signals
DMA signals
Auto 485 turn-around
Versatile interrupt system
Single interrupt output with eight maskable interrupting
conditions
Output port can be configured to provide a total of up to six
separate wire-ORable interrupt outputs
Maximum data transfer: 1× – 1 MB/sec; 16× – 125 kB/sec
Automatic wake-up mode for multidrop applications
Start-end break interrupt/status
Detects break which originates in the middle of a character
On-chip crystal oscillator
Single +5 V power supply
Commercial and industrial temperature ranges available
DIP and PLCC packages
ORDERING INFORMATION
Type number
Package
Name
Description
Commercial; VCC = +5 V ± 5%; Tamb = 0 °C to +70 °C
SCC2681AC1A44 PLCC44
plastic leaded chip carrier; 44 leads
SCC2681AC1N28 DIP28
plastic dual in-line package; 28 leads (600 mil)
SCC2681AC1N40 DIP40
plastic dual in-line package; 40 leads (600 mil)
Industrial; VCC = +5 V ± 10%; Tamb = –40 °C to +85 °C
SCC2681AE1A44 PLCC44
plastic leaded chip carrier; 44 leads
SCC2681AE1N28 DIP28
plastic dual in-line package; 28 leads (600 mil)
SCC2681AE1N40 DIP40
plastic dual in-line package; 40 leads (600 mil)
2004 Apr 06
2
Version
SOT187-2
SOT117-1
SOT129-1
SOT187-2
SOT117-1
SOT129-1









No Preview Available !

SCC2681 Даташит, Описание, Даташиты
Philips Semiconductors
Dual asynchronous receiver/transmitter (DUART)
Product data
SCC2681
PIN CONFIGURATIONS
A0 1
IP3 2
40 VCC
39 IP4
A1 3
38 IP5
IP1 4
37 IP6
A2 5
36 IP2
A3 6
35 CEN
IP0 7
34 RESET
WRN 8
33 X2
RDN 9
32 X1/CLK
RXDB 10
31 RXDA
DIP
TXDB 11
30 TXDA
OP1 12
29 OP0
OP3 13
28 OP2
OP5 14
27 OP4
OP7 15
D1 16
26 OP6
25 D0
D3 17
24 D2
D5 18
23 D4
D7 19
22 D6
GND 20
21 INTRN
A0 1
A1 2
A2 3
28 VCC
27 IP2
26 CEN
A3 4
25 RESET
WRN 5
24 X2
RDN 6
23 X1/CLK
RXDB 7
TXDB 8
22 RXDA
DIP
21 TXDA
OP1 9
20 OP0
D1 10
19 D0
D3 11
18 D2
D5 12
17 D4
D7 13
16 D6
GND 14
15 INTRN
INDEX
CORNER
7
6
1 40
39
PLCC
17
18
TOP VIEW
29
28
PIN/FUNCTION
1 NC
2 A0
3 IP3
4 A1
5 IP1
6 A2
7 A3
8 IP0
9 WRN
10 RDN
11 RXDB
12 NC
13 TXDB
14 OP1
15 OP3
16 OP5
17 OP7
18 D1
19 D3
20 D5
21 D7
22 GND
PIN/FUNCTION
23 NC
24 INTRN
25 D6
26 D4
27 D2
28 D0
29 OP6
30 OP4
31 OP2
32 OP0
33 TXDA
34 NC
35 RXDA
36 X1/CLK
37 X2
38 RESET
39 CEN
40 IP2
41 IP6
42 IP5
43 IP4
44 VCC
SD00723
PIN DESCRIPTION
PIN
SYMBOL
PLCC44 DIP40
D0–D7
28, 18,
27, 19,
26, 20,
25, 21
25, 16,
24, 17,
23, 18,
22, 19
CEN
39 35
WRN
RDN
98
10 9
A0–A3
RESET
2, 4, 6, 7
38
1, 3, 5,
6
34
INTRN
X1/CLK
24
36
21
32
Figure 1. Pin configurations
DIP28
19, 10,
18, 11,
17, 12,
16, 13
26
5
6
1–4
25
15
23
TYPE
NAME AND FUNCTION
I/O Data Bus: Bidirectional 3-State data bus used to transfer commands, data and status
between the DUART and the CPU. D0 is the least significant bit.
I Chip Enable: Active-LOW input signal. When LOW, data transfers between the CPU
and the DUART are enabled on D0-D7 as controlled by the WRN, RDN and A0-A3
inputs. When HIGH, places the D0-D7 lines in the 3-State condition.
I Write Strobe: When LOW and CEN is also LOW, the contents of the data bus is
loaded into the addressed register. The transfer occurs on the rising edge of the signal.
I Read Strobe: When LOW and CEN is also LOW, causes the contents of the
addressed register to be presented on the data bus. The read cycle begins on the
falling edge of RDN.
I Address Inputs: Select the DUART internal registers and ports for read/write
operations.
I Reset: A HIGH level clears internal registers (SRA, SRB, IMR, ISR, OPR, OPCR), puts
OP0–OP7 in the HIGH state, stops the counter/timer, and puts Channels A and B in the
inactive state, with the TxDA and TxDB outputs in the mark (HIGH) state. Clears Test
modes, sets MR pointer to MR1.
O Interrupt Request: Active-LOW, open-drain, output which signals the CPU that one or
more of the eight maskable interrupting conditions are true.
I Crystal 1: Crystal connection or an external clock input. A crystal of a clock the
appropriate frequency (nominally 3.6864 MHz) must be supplied at all times. For crystal
connections see Figure 7, Clock Timing.
2004 Apr 06
3










Скачать PDF:

[ SCC2681.PDF Даташит ]

Номер в каталогеОписаниеПроизводители
SCC2681Dual asynchronous receiver/transmitterNXP Semiconductors
NXP Semiconductors

Номер в каталоге Описание Производители
TL431

100 мА, регулируемый прецизионный шунтирующий регулятор

Unisonic Technologies
Unisonic Technologies
IRF840

8 А, 500 В, N-канальный МОП-транзистор

Vishay
Vishay
LM317

Линейный стабилизатор напряжения, 1,5 А

STMicroelectronics
STMicroelectronics

DataSheet26.com    |    2020    |

  Контакты    |    Поиск