PDF NT5SV32M8BS Data sheet ( Hoja de datos )

Número de pieza	NT5SV32M8BS
Descripción	(NT5SVxxMxxBx) 256Mb SDRAM
Fabricantes	Nanya Technology
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No Preview Available ! www.DataSheet4U.com NT5SV64M4BS / NT5SV64M4BT NT5SV32M8BS / NT5SV32M8BT NT5SV16M16BS / NT5SV16M16BT 256Mb Synchronous DRAM Features • High Performance: fCK Clock Frequency tCK Clock Cycle tAC Clock Access Time1 tAC Clock Access Time2 6K CL=3 75B CL=3 Units 166 133 MHz 6 7.5 ns — — ns 5 5.4 ns 1. Terminated load. See AC Characteristics on page 37 2. Unterminated load. See AC Characteristics on page 37 3. tRP = tRCD = 2 CKs • Single Pulsed RAS Interface • Fully Synchronous to Positive Clock Edge • Four Banks controlled by BA0/BA1 (Bank Select) • Programmable CAS Latency: 2, 3 • Programmable Burst Length: 1, 2, 4, 8 • Programmable Wrap: Sequential or Interleave • Multiple Burst Read with Single Write Option • Automatic and Controlled Precharge Command • Data Mask for Read/Write control (x4, x8) • Dual Data Mask for byte control (x16) • Auto Refresh (CBR) and Self Refresh • Suspend Mode and Power Down Mode • Standard Power operation • 8192 refresh cycles/64ms • Random Column Address every CK (1-N Rule) • Single 3.3V ± 0.3V Power Supply • LVTTL compatible • Package: 54-pin 400 mil TSOP-Type II • Lead-free & Halogen-free product available Description The NT5SV64M4BS, NT5SV64M4BT, NT5SV32M8BS, NT5SV32M8BT, NT5SV16M16BS, and NT5SV16M16BT are four-bank Synchronous DRAMs organized as 16Mbit x 4 I/O x 4 Bank, 8Mbit x 8 I/O x 4 Bank, and 4Mbit x 16 I/O x 4 Bank, respectively. These synchronous devices achieve high-speed data transfer rates of up to 166MHz by employing a pipeline chip architecture that synchronizes the output data to a system clock. The device is designed to comply with all JEDEC standards set for synchronous DRAM products, both electrically and mechanically. All of the control, address, and data input/out- put (I/O or DQ) circuits are synchronized with the positive edge of an externally supplied clock. RAS, CAS, WE, and CS are pulsed signals which are exam- ined at the positive edge of each externally applied clock (CK). Internal chip operating modes are defined by combina- tions of these signals and a command decoder initiates the necessary timings for each operation. A fifteen bit address bus accepts address data in the conventional RAS/CAS mul- tiplexing style. Thirteen row addresses (A0-A12) and two bank select addresses (BA0, BA1) are strobed with RAS. Eleven column addresses (A0-A9, A11) plus bank select addresses and A10 are strobed with CAS. Column address A11 is dropped on the x8 device, and column addresses A11 and A9 are dropped on the x16 device. Prior to any access operation, the CAS latency, burst length, and burst sequence must be programmed into the device by address inputs A0-A12, BA0, BA1 during a mode register set cycle. In addition, it is possible to program a multiple burst sequence with single write cycle for write through cache operation. Operating the four memory banks in an interleave fashion allows random access operation to occur at a higher rate than is possible with standard DRAMs. A sequential and gap- less data rate of up to 166MHz is possible depending on burst length, CAS latency, and speed grade of the device. Auto Refresh (CBR) and Self Refresh operation are sup- ported. REV 1.4 Oct 2006 1 © NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice. 1 page www.DataSheet4U.com NT5SV64M4BS / NT5SV64M4BT NT5SV32M8BS / NT5SV32M8BT NT5SV16M16BS / NT5SV16M16BT 256Mb Synchronous DRAM Block Diagram CKE CKE Buffer CK CK Buffer A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A11 A12 BA1 BA0 A10 Column Decoder Cell Array Memory Bank 0 Sense Amplifiers Column Decoder Cell Array Memory Bank 1 Sense Amplifiers DQ0 DQX CS RAS CAS WE Column Decoder Cell Array Memory Bank 2 Sense Amplifiers DQM Column Decoder Cell Array Memory Bank 3 Sense Amplifiers Cell Array, per bank, for 16Mb x 4 DQ: 8192 Row x 2048 Col x 4 DQ (DQ0-DQ3). Cell Array, per bank, for 8Mb x 8 DQ: 8192 Row x 1024 Col x 8 DQ (DQ0-DQ7). Cell Array, per bank, for 4Mb x 16 DQ: 8192 Row x 512 Col x 16 DQ (DQ0-DQ15). REV 1.4 Oct 2006 5 © NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice. 5 Page www.DataSheet4U.com NT5SV64M4BS / NT5SV64M4BT NT5SV32M8BS / NT5SV32M8BT NT5SV16M16BS / NT5SV16M16BT 256Mb Synchronous DRAM Burst Read Command The Burst Read command is initiated by having CS and CAS low while holding RAS and WE high at the rising edge of the clock. The address inputs determine the starting column address for the burst, the Mode Register sets the type of burst (sequential or interleave) and the burst length (1, 2, 4, 8). The delay from the start of the command to when the data from the first cell appears on the outputs is equal to the value of the CAS latency that is set in the Mode Register. Burst Read Operation (Burst Length = 4, CAS latency = 2, 3) T0 T1 T2 T3 T4 T5 T6 T7 T8 CK COMMAND READ A NOP NOP NOP NOP NOP NOP NOP NOP CAS latency = 2 tCK2, DQs CAS latency = 3 tCK3, DQs DOUT A0 DOUT A1 DOUT A2 DOUT A3 DOUT A0 DOUT A1 DOUT A2 DOUT A3 Read Interrupted by a Read A Burst Read may be interrupted before completion of the burst by another Read Command, with the only restriction being that the interval that separates the commands must be at least one clock cycle. When the previous burst is interrupted, the remain- ing addresses are overridden by the new address with the full burst length. The data from the first Read Command continues to appear on the outputs until the CAS latency from the interrupting Read Command is satisfied, at this point the data from the interrupting Read Command appears. Read Interrupted by a Read (Burst Length = 4, CAS latency = 2, 3) T0 T1 T2 T3 T4 T5 T6 T7 T8 CK COMMAND READ A READ B NOP NOP NOP NOP NOP NOP NOP CAS latency = 2 tCK2, DQs CAS latency = 3 tCK3, DQs DOUT A0 DOUT B0 DOUT B1 DOUT B2 DOUT B3 DOUT A0 DOUT B0 DOUT B1 DOUT B2 DOUT B3 REV 1.4 Oct 2006 11 © NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice. 11 Page

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