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PDF NTD2955 Data sheet ( Hoja de datos )

Número de pieza NTD2955
Descripción Power MOSFET ( Transistor )
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NTD2955
Power MOSFET
−60 V, −12 A, P−Channel DPAK
This Power MOSFET is designed to withstand high energy in the
avalanche and commutation modes. Designed for low−voltage, high−
speed switching applications in power supplies, converters, and power
motor controls. These devices are particularly well suited for bridge
circuits where diode speed and commutating safe operating areas are
critical and offer an additional safety margin against unexpected
voltage transients.
Features
Avalanche Energy Specified
IDSS and VDS(on) Specified at Elevated Temperature
Designed for Low−Voltage, High−Speed Switching Applications and
to Withstand High Energy in the Avalanche and Commutation Modes
Pb−Free Packages are Available
MAXIMUM RATINGS (TJ = 25°C unless otherwise noted)
Rating
Symbol Value Unit
Drain−to−Source Voltage
Gate−to−Source Voltage
− Continuous
− Non−repetitive (tp 10 ms)
Drain Current
Drain Current − Continuous @ Ta = 25°C
Drain Current − Single Pulse (tp 10 ms)
Total Power Dissipation @ Ta = 25°C
Operating and Storage Temperature
Range
VDSS
VGS
VGSM
−60
± 20
± 25
ID
IDM
PD
TJ, Tstg
−12
−36
55
−55 to
175
Vdc
Vdc
Vpk
Adc
Apk
W
°C
Single Pulse Drain−to−Source Avalanche
Energy − Starting TJ = 25°C
(VDD = 25 Vdc, VGS = 10 Vdc, Peak
IL = 12 Apk, L = 3.0 mH, RG = 25 W)
Thermal Resistance
− Junction−to−Case
− Junction−to−Ambient (Note 1)
− Junction−to−Ambient (Note 2)
EAS
RqJC
RqJA
RqJA
216 mJ
2.73 °C/W
71.4
100
Maximum Lead Temperature for Soldering
Purposes, 1/8 in. from case for
10 seconds
TL
260 °C
Maximum ratings are those values beyond which device damage can occur.
Maximum ratings applied to the device are individual stress limit values (not
normal operating conditions) and are not valid simultaneously. If these limits
are exceeded, device functional operation is not implied, damage may occur
and reliability may be affected.
1. When surface mounted to an FR4 board using 1 in pad size
(Cu area = 1.127 in2).
2. When surface mounted to an FR4 board using the minimum recommended
pad size (Cu area = 0.412 in2).
http://onsemi.com
V(BR)DSS
−60 V
RDS(on) TYP
155 mW @ −10 V, 6 A
ID MAX
−12 A
P−Channel
D
G
S
MARKING
DIAGRAMS
4
12
3
4
4
Drain
DPAK
CASE 369C
STYLE 2
1
Gate
2
Drain
3
Source
4
Drain
DPAK−3
CASE 369D
STYLE 2
1
2
3
12 3
Gate Drain Source
NT2955
A
Y
W
Device Code
= Assembly Location
= Year
= Work Week
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 6 of this data sheet.
© Semiconductor Components Industries, LLC, 2005
May, 2005 − Rev. 8
1
Publication Order Number:
NTD2955/D

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NTD2955 pdf
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1.0
D = 0.5
0.2
0.1
0.1 0.05
0.01
1.0E−05
0.02
0.01
SINGLE PULSE
1.0E−04
NTD2955
P(pk)
t1
t2
DUTY CYCLE, D = t1/t2
1.0E−03
1.0E−02
t, TIME (s)
1.0E−01
Figure 13. Thermal Response
RqJC(t) = r(t) RqJC
D CURVES APPLY FOR POWER
PULSE TRAIN SHOWN
READ TIME AT t1
TJ(pk) − TC = P(pk) RqJC(t)
1.0E+00
1.0E+01
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