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PDF CD40xxB Data sheet ( Hoja de datos )
| Número de pieza | CD40xxB | |
| Descripción | (CD4000B Series) Technical Overview | |
| Fabricantes | Harris Semiconductor | |
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Technical Overview
CD4000B Series
This section is intended as a guide for circuit and equipment
designers in the operation and application of MOS inte-
grated circuits. It covers general operating and handling con-
siderations with respect to the following critical factors:
• Operating Supply Voltage Range
• Power Dissipation and Derating
• System Noise Considerations
• Power Source Rules
• Gate-oxide Protection Networks
• Input Signals and Ratings
• Chip Assembly and Storage
• Device Mounting
• Testing
More specific information is then given on significant fea-
tures, special design and application requirements, and
standard ratings and electrical characteristics for CMOS B-
series logic circuits, and on CMOS special function circuits
(special interface and display driver circuits).
General Operating and Handling
Considerations
The following paragraphs discuss some key operating and
handling considerations that must be taken into account to
achieve maximum advantage of the CMOS technology.
Additional information on the operation and handling of
CMOS integrated circuits is given in Application Note
AN6525, “Guide to Better Handling and Operation of CMOS
Integrated Circuits”. See Section 8, “How to Use Answer-
FAX”, in this selection guide.
Operating Supply Voltage Range
Because logic systems occasionally experience transient con-
ditions on the power supply line which, when added to the
nominal power-bus voltage, could exceed the safe limits of cir-
cuits connected to the power bus, the recommended operat-
ing supply voltage range is 3V to 18V for B-series devices.
The recommended maximum power supply limit is substan-
tially below the minimum primary breakdown limit for the
devices to allow for limited power supply transient and regula-
tion limits. For circuits that operated in a linear mode over a
portion of the voltage range, such as RC or crystal oscillators,
a minimum supply voltage of 4V is recommended.
Power Dissipation and Derating
The power dissipation of a CMOS integrated circuit is the
sum of a DC (quiescent) component and an AC (dynamic)
components. The DC component is the sum of the net inte-
grated circuit reverse diode junction current and the surface
leakage current times the supply voltage. In standard B-
series logic devices, the DC dissipation typically ranges,
depending upon device complexity, from 100nW to 400nW
for a supply voltage of 10V. Worst-case DC dissipation is the
product of the maximum quiescent current (given in the data
sheet on each device) and the DC supply voltage VDD.
Dynamic power dissipation has three components:
1. The dissipation that results from current that charges and
discharges the external load capacitance of the output
buffers. The dissipation of each output buffer is equal to
CV2f, where C is the load capacitance, V is the supply
voltage, and f is the switching frequency of that output.
2. The dissipation that results from current that charges and
discharges the internal node capacitances.
3. The dissipation caused by the current spikes through the
PMOS and NMOS transistors in series at the instant of
switching. This component amounts to approximately
10% of the total dissipation, shown graphically in the
datasheets of most CMOS circuits.
All CMOS devices are rated at 200mW per package at the
maximum operating ambient temperature rating (TA) of
125oC for all packages. Power ratings for temperatures
below the maximum operating temperature are shown in the
standard CMOS thermal derating chart in Figure 1. This
chart assumes that the device is mounted and soldered (or
placed in a socket) on a PC board; there is natural convec-
tion cooling, with the PC board mounted horizontally; and
the pressure is standard (14.7psia). In addition to the overall
package dissipation, device dissipation per output transistor
is limited to 100mW maximum over the full package operat-
ing temperature range.
SLOPE = 12mW/oC
600
500
400
300
200
100
20 40 60 80 85 100
TA, AMBIENT TEMPERATURE (oC)
120 125
FIGURE 1. STANDARD CMOS THERMAL DERATING CHART
System Noise Considerations
In general, CMOS devices are much less sensitive to noise
on power and ground lines than bipolar logic families (such
as TTL or DTL). However, this sensitivity varies as a function
of the power supply voltage, and more importantly as a func-
tion of synchronism between noise spikes and input transi-
tions. Good power distribution in digital systems requires
that the power bus have a low dynamic impedance; for this
purpose, discrete decoupling capacitors should be distrib-
uted across the power bus. A more detailed discussion of
CMOS noise immunity is provided by Application Note
AN6587, “Noise Immunity of B-series CMOS Integrated Cir-
cuits”. See Section 8, “How to Use AnswerFAX”, in this
selection guide.
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Technical Overview
Because of the extremely small size and fragile nature of
chips, the equipment designer should exercise care in han-
dling these devices.
For additional handling considerations for CMOS devices,
refer to Application Note AN6525, “Guide to Better Handling
and Operation of CMOS Integrated Circuits”. See Section 8,
“How to Use AnswerFAX”, in this selection guide.
• Grounding
- Bonders, pellet pick-up tools, table tops, trim and form
tools, sealing equipment, and other equipment used in
chip handling should be properly grounded.
- The operator should be properly grounded.
• In-Process Handling
- Assemblies or subassemblies of chips should be trans-
ported and stored in conductive carriers.
- All external leads of the assemblies or subassemblies
should be shorted together.
• Bonding Sequence
- Connect VDD first to external connections, for example,
terminal 14 of the CD4001BH.
- Remaining functions may be connected to their external
connections in any sequence.
• Testing
- Transport all assemblies of chips in conductive carriers.
- In testing chip assemblies or subassemblies, the opera-
tor should be properly grounded.
Visual Inspection Criteria
All standard commercial CMOS chips undergo a visual inspec-
tion which is patterned after MIL-STD-883, Method 2010, Con-
dition B with modifications reflecting CMOS requirements.
Testing Criteria
CMOS chips are DC electrically tested 100% in accordance
with the same standards prescribed for Harris devices in
standard packages.
Device Testing
Harris CMOS circuits are 100% tested by circuit probe in the
wafer stage and are 100% tested again after they have been
packaged. DC tests of Harris devices are performed at 5V,
10V, 15V, and 20V; functionality is checked at 2.8V, 17V, and
20V. Sample testing is used to assure adherence to quality
requirements and AC specifications.
Static test, high speed functional and DC parametric tests,
are performed at wafer and package stages by means of a
Teradyne 325 test set or equivalent.
Users should follow the sequences below when testing
CMOS devices:
1. Insert the device into the test socket.
2. Apply VDD.
3. Apply the input signal.
4. Perform the test.
5. On completion of test, remove the input signal.
6. Turn off the power supply (VDD).
7. Remove the device from the test socket and insert it into
a conductive carrier. CMOS devices under test must not
be exposed to electrostatic discharge or forward biasing
of the intrinsic protective diodes shown in Figure 3.
Detailed information on the techniques employed in the test-
ing of Harris CMOS integrated circuits are described in
Application Note AN6532, “Fundamentals of Testing CMOS
Integrated Circuits”. See Section 8, “How to Use Answer-
FAX”, in this selection guide.
Device Mounting
Integrated circuits are normally supplied with lead-tin plated
leads to facilitate soldering into circuit boards. In those rela-
tively few applications requiring welding of the device leads,
rather than soldering, the devices may be obtained with
nickel-plated Kovar leads (See MIL-I-38535). It should be
recognized that this type of plating will not provide complete
protection against lead corrosion in the presence of high
humidity and mechanical stress.
In any method of mounting integrated circuits which involves
bending or forming of the device leads, it is extremely impor-
tant that the lead be supported and clamped between the
bend and the package seal, and that bending be done with
care to avoid damage to lead plating. In no case should the
radius of the bend be less than the diameter of the lead. It is
also extremely important that the ends of bent leads be
straight to assure proper insertion through the holes in the
printed-circuit board.
High Voltage B-Series CMOS
Integrated Circuits
Harris CD4000B series types have a maximum DC supply
voltage rating of -0.5V to 20V, and a recommended operat-
ing supply voltage range of 3V to 18V. The major features of
this series are as follows:
• High Voltage (20V) Ratings
• 100% Tested for Quiescent Current at 20V
• 5V, 10V, and 15V Parametric Ratings
• Standardized, Symmetrical Output Characteristics
• Maximum Input Current of 1µA at 18V Over Full Package
Temperature Range; 100nA at 18V and 25oC
• Noise Margin (Full Package Temperature Range) =
1V at VDD = 5V
2V at VDD = 10V
2.5 V at VDD = 15V
• Meets all requirements of JEDEC Tentative Standard No.
13B, “Standard Specifications for Description of B-Series
CMOS Devices”.
JEDEC Minimum Standard
Under the sponsorship of the Joint Electron Devices Engi-
neering Council (JEDEC) of the Electronic Industries Associ-
ation (EIA), minimum industrial standards have been
established for the maximum ratings, DC and AC electrical
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Family Ratings and Specifications‡
DC Electrical Specification JEDEC Standard for DC Specifications of B-Series CMOS Integrated Circuits (Continued)
TEST
TEMP. VDD
PARAMETERS SYMBOL CONDITIONS RANGE (V)
Input Low Voltage
B Types
VIL VO = 0.5V or 4.5V All
VO = 1V or 9V
VO = 1.5V or 13.5V
|IO| <1µA
5
10
15
UB Types
5
10
15
(NOTE 3)
TLOW
MIN MAX
- 1.5
-3
-4
-1
-2
- 2.5
+25oC
MIN TYP MAX
- - 1.5
- -3
- -4
- -1
- -2
- - 2.5
(NOTE 4)
THIGH
MIN MAX
UNIT
- 1.5 V
- 3V
- 4V
- 1V
- 2V
- 2.5 V
Input High Voltage VIH VO = 0.5V or 4.5V All
5 3.5 - 3.5 -
B Types
VO = 1V or 9V
VO = 1.5V or 13.5V
10 7 - 7 -
|IO| <1µA
15 11 - 11 -
UB Types
54 - 4 -
- 3.5 -
-7-
- 11 -
-4-
V
V
V
V
10 8 - 8 -
15 12.5 - 12.5 -
Output Low (Sink)
IOL VO = 0.4V
Mil 5 0.64 - 0.51 -
Current
VIN = 0V or 5V
VO = 0.5V
10 1.6 - 1.3 -
VIN = 0V or 10V
VO = 1.5V
15 4.2 - 3.4 -
VIN = 0V or 15V
Comm
5
0.52
-
0.44
-
10 1.3 - 1.1 -
15 3.6 - 3.0 -
-8-
- 12.5 -
- 0.36 -
- 0.9 -
- 2.4 -
- 0.36 -
- 0.9 -
- 2.4 -
V
V
mA
mA
mA
mA
mA
mA
Output High
(Source) Current
IOH VO = 4.6V
Mil 5 -0.25 - -0.2 -
VIN = 0V or 5V
VO = 9.5V
10 -0.62 - -0.5 -
VIN = 0V or 10V
VO = 13.5V
15 -1.8 - -1.5 -
VIN = 0V or 15V
Comm
5
-0.2
- -0.16 -
- -0.14 -
- -0.35 -
- -1.1 -
- -0.12 -
mA
mA
mA
mA
10 -0.5 - -0.4 -
- -0.3 -
15 -1.4 - -1.2 -
- -1.0 -
Input Current
Three-State
Output Leakage
Current
IIN VIN = 0V or 15V
VIN = 0V or 15V
IOUT Max VIN = 0V or 15V
VIN = 0V or 15V
Mil
Comm
Mil
Comm
15
15
15
15
- ±0.1 -
- ±0.3 -
- ±0.4 -
- ±1.6 -
- ±0.1 -
±1
- ±0.3 -
±1
- ±0.4 - ±12
- ±1.6 - ±12
Input Capacitance
Per Unit Load
CIN Any Input
All - - - - - 7.5 - -
NOTES:
1. Voltages referenced to VSS.
2. Reprinted from JEDEC Standard No. 13-B, “JEDEC Standard Specification for Description of B-Series CMOS Devices”.
3. TLOW = -55oC for Military Temperature Range Device, -40oC for Commercial Temperature Device (All Harris Devices).
4. THIGH = +125oC for Military Temperature Range Device, +85oC for Commercial Temperature Range Device.
mA
mA
µA
µA
µA
µA
pF
‡ For specific technical information on each individual device type, refer to the appropriate data sheet in Harris AnswerFAX.
See Section 8, “How to use AnswerFAX”, in this selection guide.
5-13
11 Page | ||
| Páginas | Total 16 Páginas | |
| PDF Descargar | [ Datasheet CD40xxB.PDF ] | |
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