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PDF 6168LA70DB Data sheet ( Hoja de datos )

Número de pieza 6168LA70DB
Descripción IDT6168LA70DB
Fabricantes IDT 
Logotipo IDT Logotipo



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CMOS Static RAM
16K (4K x 4-Bit)
IDT6168SA
IDT6168LA
Features
x High-speed (equal access and cycle time)
– Military: 25/45ns (max.)
– Industrial: 25ns (max.)
– Commercial: 15/20/25ns (max.)
x Low power consumption
x Battery backup operation—2V data retention voltage
www.DataSheet4U(.IcDoTm6168LA only)
x Available in high-density 20-pin ceramic or plastic DIP and
20-pin leadless chip carrier (LCC)
x Produced with advanced CMOS high-performance
technology
x CMOS process virtually eliminates alpha particle
soft-error rates
x Bidirectional data input and output
x Military product compliant to MIL-STD-883, Class B
Description
The IDT6168 is a 16,384-bit high-speed static RAM organized
as 4K x 4. It is fabricated using lDT’s high-performance, high-reliability
CMOS technology. This state-of-the-art technology, combined with inno-
vative circuit design techniques, provides a cost-effective approach for
high-speed memory applications.
Access times as fast 15ns are available. The circuit also offers a
reduced power standby mode. When CS goes HIGH, the circuit will
automatically go to, and remain in, a standby mode as long as CS remains
HIGH. This capability provides significant system-level power and cooling
savings. The low-power (LA) version also offers a battery backup data
retention capability where the circuit typically consumes only 1µW
operating off a 2V battery. All inputs and outputs of the IDT6168 are
TTL-compatible and operate from a single 5V supply.
The IDT6168 is packaged in either a space saving 20-pin, 300-mil
ceramic or plastic DIP or a 20-pin LCC providing high board-level
packing densities.
Military grade product is manufactured in compliance with the
latest revision of MIL-STD-883, Class B, making it ideally suited to
military temperature applications demanding the highest level of
performance and reliability.
Functional Block Diagram
A0
ADDRESS
DECODER
16,384-BIT
MEMORY ARRAY
VCC
GND
A11
I/O0
I/O CONTROL
I/O1
INPUT
DATA
I/O2 CONTROL
I/O3
,
CS
WE
©2000 Integrated Device Technology, Inc.
1
3090 drw 01
FEBRUARY 2001
DSC-3090/05

1 page




6168LA70DB pdf
IDT6168SA/LA
CMOS Static RAM 16K (4K x 4-Bit)
Military, Industrial, and Co mmercial Temperature Ranges
AC Electrical Characteristics (VCC = 5.0V ± 10%, All Temperature Ranges)
6168SA15(1)
6168SA20(1)
6168LA20(1)
6168SA25
6168LA25
6168SA45(2)
6168LA45(2)
Symbol
Parameter
Min. Max. Min. Max. Min. Max. Min. Max. Unit
Read Cycle
tRC Read Cycle Time
15 ____ 20 ____ 25 ____ 45 ____ ns
tAA Address Access Time
____ 15 ____ 20 ____ 25 ____ 45 ns
tACS Chip Select Access Time
____ 15 ____ 20 ____ 25 ____ 45 ns
tCLZ(3)
Chip Select to Output in Low-Z
3 ____ 5 ____ 5 ____ 5 ____ ns
www.DataSheett4CUHZ.(3c)om
tOH
Chip Desele ct to Output in High-Z
Output Hold from Address Change
____ 8 ____ 10 ____ 10 ____ 25 ns
3 ____ 3 ____ 3 ____ 3 ____ ns
tPU(3) Chip Sele ct to Power Up Time
0 ____ 0 ____ 0 ____ 0 ____ ns
tPD(3) Chip Deselect to Power Down Time
____ 35 ____ 20 ____ 25 ____ 40 ns
NOTES:
1. 0° to +70°C temperature range only.
2. –55°C to +125°C temperature range only.
3. This parameter is guaranteed with AC Test load (Figure 2) by device characterization, but is not production tested.
3090 tbl 12
Timing Waveform of Read Cycle No. 1(1, 2)
tRC
ADDRESS
DATAOUT
tAA
tOH
PREVIOUS DATA VALID
Timing Waveform of Read Cycle No. 2(1, 3)
tRC
CS
DATAOUT
VCC
ICC
SUPPLY
CURRENT
ISB
tACS
tCLZ (4)
HIGH IMPEDANCE
tPU
NOTES:
1. WE is HIGH for Read cycle.
2. CS is LOW for Read cycle.
3. Device is continuously selected, CS is LOW.
3. Address valid prior to or coincident with CS transition LOW.
4. Transition is measured ±200mV from steady state.
6.452
DATA VALID
,3090 drw 06
tCHZ (3)
DATAOUT VALID
tPD
HIGH IMPEDANCE
3090 drw 07
,

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