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PDF 74FCT574A Data sheet ( Hoja de datos )
| Número de pieza | 74FCT574A | |
| Descripción | FAST CMOS OCTAL D REGISTERS | |
| Fabricantes | IDT | |
| Logotipo |  |
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IDT54/74FCT574/A/C
FAST CMOS OCTAL D REGISTER (3-STATE)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
FAST CMOS OCTAL
D REGISTERS (3-STATE)
IDT54/74FCT574/A/C
FEATURES:
− IDT54/74FCT574 equivalent to FAST™ speed and drive
− IDT54/74FCT574A up to 30% faster than FAST
− IDT54/74FCT574C up to 50% faster than FAST
www.Data−SheeItO4LU=.c4om8mA (commercial) and 32mA (military)
− CMOS power levels (1mW typ. static)
− Edge triggered master/slave, D-type flip-flops
− Buffered common clock and buffered common three-state control
− Military product compliant to MIL-STD-883, Class B
− Meets or exceeds JEDEC Standard 18 specifications
− Available in the following packages:
• Commercial: SOIC
• Military: CERDIP, LCC, CERPACK
DESCRIPTION:
The FCT574 is an 8-bit register built using an advanced dual metal CMOS
technology. These registers consist of eight D-type flip-flops with a buffered
common clock and buffered 3-state output control. When the output enable
(OE) is low, the eight outputs are enabled. When the OE input is high, the
outputs are in the high-impedance state.
Input data meeting the set-up and hold time requirements of the D inputs
is transferred to the O outputs on the low-to-high transition of the clock input.
The FCT574 has non-inverting outputs with respect to the data at the D
inputs.
FUNCTIONAL BLOCK DIAGRAM
D0 D1 D2 D3 D4 D5 D6 D7
CP
CP D
CP D
CP D
CP D
CP D
CP D
CP D
CP D
Q QQ QQ Q Q Q
OE
O0 O1 O2 O3 O4 O5 O6 O7
MILITARY AND COMMERCIAL TEMPERATURE RANGES
c 1999 Integrated Device Technology, Inc.
1
JUNE 2000
DSC-5428/-
1 page  
IDT54/74FCT574/A/C
FAST CMOS OCTAL D REGISTER (3-STATE)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
54/74FCT574
Com'l.
Mil.
54/74FCT574A
Com'l.
Mil.
54/74FCT574C
Com'l.
Mil.
Symbol
Parameter
Conditions(1) Min.(2) Max. Min.(2) Max. Min.(2) Max. Min.(2) Max. Min.(2) Max. Min.(2) Max.
tPLH Propagation Delay
tPHL CP to ON
CL = 50pF
RL = 500Ω
2 10 2 11 2 6.5 2 7.2 2 5.2 2 6.2
tPZH Output Enable Time
tPZL
1.5 12.5 1.5 14 1.5 6.5 1.5 7.5 1.5 5.5 1.5 6.2
tPHZ Output Disable Time
tPLZ
1.5 8 1.5 8 1.5 5.5 1.5 6.5 1.5 5 1.5 5.7
tSU Set-up Time HIGH
w w w . D a t a S h e eortL4OUW,. DcNotomCP
tH Hold Time HIGH
or LOW, DN to CP
2—2—2—2—2—2—
1.5 — 1.5 — 1.5 — 1.5 — 1.5 — 1.5 —
tW CP Pulse Width
HIGH or LOW
7—7—5—6—5—6—
NOTES:
1. See test circuit and waveforms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
Unit
ns
ns
ns
ns
ns
ns
5
5 Page | ||
| Páginas | Total 7 Páginas | |
| PDF Descargar | [ Datasheet 74FCT574A.PDF ] | |
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