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PDF 74AC273 Data sheet ( Hoja de datos )
| Número de pieza | 74AC273 | |
| Descripción | Octal D Flip-Flop | |
| Fabricantes | ON Semiconductor | |
| Logotipo |  |
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MC74AC273, MC74ACT273
Octal D Flip−Flop
The MC74AC273/74ACT273 has eight edge-triggered D−type
flip−flops with individual D inputs and Q outputs. The common
buffered Clock (CP) and Master Reset (MR) inputs load and reset
(clear) all flip−flops simultaneously.
The register is fully edge-triggered. The state of each D input, one
setup time before the LOW−to−HIGH clock transition, is transferred
to the corresponding flip−flop’s Q output.
All outputs will be forced LOW independently of Clock or Data
inputs by a LOW voltage level on the MR input. The device is useful
www.DataSheet4fUor.caopmplications where the true output only is required and the Clock
and Master Reset are common to all storage elements.
Features
• Ideal Buffer for MOS Microprocessor or Memory
• Eight Edge-Triggered D Flip−Flops
• Buffered Common Clock
• Buffered, Asynchronous Master Reset
• See MC74AC377 for Clock Enable Version
• See MC74AC373 for Transparent Latch Version
• See MC74AC374 for 3-State Version
• Outputs Source/Sink 24 mA
• ′ACT273 Has TTL Compatible Inputs
• Pb−Free Packages are Available*
VCC Q7 D7 D6 Q6 Q5 D5 D4 Q4 CP
20 19 18 17 16 15 14 13 12 11
1 2 3 4 5 6 7 8 9 10
MR Q0 D0 D1 Q1 Q2 D2 D3 Q3 GND
(Top View)
Pinout: 20−Lead Packages Conductors
http://onsemi.com
20
1
20
1
PDIP−20
SUFFIX N
CASE 738
SOIC−20WB
SUFFIX DW
CASE 751D
20
1
TSSOP−20
SUFFIX DT
CASE 948E
20
1
SOEIAJ−20
SUFFIX M
CASE 967
PIN ASSIGNMENT
PIN
D0−D7
MR
CP
FUNCTION
Data Inputs
Master Reset
Clock Pulse Input
Q0−Q7
Data Outputs
MODE SELECT-FUNCTION TABLE
Operating Mode
Reset (Clear)
Inputs
MR CP
LX
Dn
X
Load ′1′
HH
Load ′0′
HL
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
= LOW-to-HIGH Clock Transition
Outputs
Qn
L
H
L
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
© Semiconductor Components Industries, LLC, 2005
December, 2005 − Rev. 6
1
D0 D1 D2 D3 D4 D5 D6 D7
CP
MR
Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
Logic Symbol
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 5 of this data sheet.
DEVICE MARKING INFORMATION
See general marking information in the device marking
section on page 6 of this data sheet.
Publication Order Number:
MC74AC273/D
1 page  
MC74AC273, MC74ACT273
ORDERING INFORMATION
Device
MC74AC273N
Package
PDIP−20
Shipping†
18 Units / Rail
MC74AC273NG
PDIP−20
(Pb−Free)
18 Units / Rail
MC74ACT273N
PDIP−20
18 Units / Rail
MC74ACT273NG
PDIP−20
(Pb−Free)
18 Units / Rail
MC74AC273DW
SOIC−20WB
38 Units / Rail
MC74AC273DWG
SOIC−20WB
(Pb−Free)
38 Units / Rail
MC74AC273DWR2
SOIC−20WB
1000 / Tape & Reel
MC74AC273DWR2G
www.DataSheet4U.com
SOIC−20WB
(Pb−Free)
1000 / Tape & Reel
MC74AC273DTR2
TSSOP−20*
2500 / Tape & Reel
MC74AC273DTR2G
TSSOP−20*
2500 / Tape & Reel
MC74ACT273DW
SOIC−20WB
38 Units / Rail
MC74ACT273DWG
SOIC−20WB
(Pb−Free)
38 Units / Rail
MC74ACT273DWR2
SOIC−20WB
1000 / Tape & Reel
MC74ACT273DWR2G
SOIC−20WB
(Pb−Free)
1000 / Tape & Reel
MC74ACT273DTR2
TSSOP−20*
2500 / Tape & Reel
MC74ACT273DTR2G
TSSOP−20*
2500 / Tape & Reel
MC74AC273MEL
SOEIAJ−20
2000 / Tape & Reel
MC74AC273MELG
SOEIAJ−20
(Pb−Free)
2000 / Tape & Reel
MC74ACT273M
SOEIAJ−20
40 Units / Rail
MC74ACT273MG
SOEIAJ−20
(Pb−Free)
40 Units / Rail
MC74ACT273MEL
SOEIAJ−20
2000 / Tape & Reel
MC74ACT273MELG
SOEIAJ−20
(Pb−Free)
2000 / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*This package is inherently Pb−Free.
http://onsemi.com
5
5 Page | ||
| Páginas | Total 8 Páginas | |
| PDF Descargar | [ Datasheet 74AC273.PDF ] | |
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