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PDF HM514280A Data sheet ( Hoja de datos )
| Número de pieza | HM514280A | |
| Descripción | 18-bit Dynamic Random Access Memory | |
| Fabricantes | Renesas Technology | |
| Logotipo |  |
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HM514280A/AL Series
262,144-word × 18-bit Dynamic Random Access Memory
The Hitachi HM514280A/AL are CMOS dynamic
RAM organized as 262,144-word × 18-bit.
HM514280A/AL have realized higher density,
higher performance and various functions by
employing 0.8 µm CMOS process technology and
some new CMOS circuit design technologies. The
HM514280A/AL offer fast page mode as a high
speed access mode.
Multiplexed address input permits the
HM514280A/AL to be packaged in standard 400-
www.DataShmeielt44U0.c-pomin plastic SOJ, standard 475-mil 40-pin
plastic ZIP and standard 400-mil 44-pin plastic
TSOPII.
Features
• Single 5 V (±10%)
• High speed
– Access time: 70 ns/80 ns (max)
• Low power dissipation
– Active mode: 825 mW/770 mW (max)
– Standby mode: 11 mW (max)
1.1 mW (max) (L-version)
• Fast page mode capability
• 512 refresh cycles: 8 ms
128 ms (L-version)
• 2 CAS byte control
• 2 variations of refresh
– RAS -only refresh
– CAS -before-RAS refresh
• Battery back up operation (L-version)
Ordering Information
Access
Type No.
time
Package
——————————————————————–
HM514280AJ-7
70 ns
400-mil 40-pin
HM514280AJ-8
80 ns
plastic SOJ
(CP-40D)
——————————————————————–
HM514280AZ-7
70 ns
475-mil 40-pin
HM514280AZ-8
80 ns
plastic ZIP
(ZP-40)
——————————————————————–
HM514280ATT-7
70 ns
400-mil 44-pin
HM514280ATT-8
80 ns
plastic TSOPII
(TTP-44/40DB)
——————————————————————–
HM514280ALJ-7
70 ns
400 mil 40-pin
HM514280ALJ-8
80 ns
plastic SOJ
(CP-40D)
——————————————————————–
HM514280ALZ-7
70 ns
475-mil 40-pin
HM514280ALZ-8
80 ns
plastic ZIP
(ZP-40)
——————————————————————–
HM514280ALTT-7
70 ns
400 mil 44-pin
HM514280ALTT-8
80 ns
plastic TSOPII
(TTP-44/40DB)
——————————————————————–
1
1 page  
HM514280A/AL Series
HM514280A/AL Series
Recommended DC Operating Conditions (Ta = 0 to +70°C) *2
Parameter
Symbol
Min
Typ
Max Unit Note
———————————————————————————————————————————————–
Supply voltage
VSS 0 0 0 V
———————————————————————————————–
VCC
4.5 5.0 5.5 V
1
———————————————————————————————————————————————–
Input high voltageVIH
2.4
— 6.5 V
1
———————————————————————————————————————————————–
Input low
voltage
(I/O pin)
VIL
–1.0 —
0.8 V
1
———————————————————————————————————————–
(Others)
VIL
–2.0 —
0.8 V
1
———————————————————————————————————————————————–
Notes: 1.
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All voltage referenced to VSS
The supply voltage with all VCC pins must be on the same level.
The supply voltage with all VSS pins must be on the same level.
DC Characteristics (Ta = 0 to +70°C, VCC = 5 V ± 10%, VSS = 0 V)
HM514280A/AL
————————————–
-7 -8
—————— ——————
Parameter
Symbol Min Max Min Max Unit Test conditions
Notes
———————————————————————————————————————————————–
Operating current
ICC1
— 150 — 140 mA RAS cycling
LCAS or UCAS cycling
1, 2
tRC = min
———————————————————————————————————————————————–
Standby current
ICC2
—2
—2
mA TTL interface
RAS, LCAS, UCAS = VIH
Dout = High-Z
————————————————————————————————
—1
—1
mA CMOS interface
RAS, LCAS, UCAS, WE
OE > VCC – 0.2 V
Dout = High-Z
——————————
————————————————————————————————
Standby current
(L-version)
— 200 — 200 µA CMOS interface
RAS, LCAS, OE, WE
UCAS > VCC – 0.2 V
Dout = High-Z
———————————————————————————————————————————————–
RAS-only refresh
ICC3
— 140 — 130 mA tRC = min
2
current
———————————————————————————————————————————————–
Standby current
ICC5
—5
—5
mA RAS = VIH
LCAS or UCAS = VIL
1
Dout = enable
———————————————————————————————————————————————–
CAS-before-RAS
ICC6
— 140 — 130 mA tRC = min
25
refresh current
———————————————————————————————————————————————–
5
5 Page 
HM514280A/AL Series
HM514280A/AL Series
17. When both LCAS and UCAS go low at the same time, all 18-bits data are written into the
device. LCAS and UCAS cannot be staggered within the same write/read cycles.
18. All the VCC and VSS pins shall be supplied with the same voltages.
19. tASC, tCAH, tRCS, tRCH, tWCS, tWCH, tCSR and tRPC are determined by the earlier falling edge
of UCAS or LCAS.
20. tCRP, tCHR, tACP and tCPW are determined by the later rising edge of UCAS or LCAS.
21. tCWL, tDH, tDS and tCHS should be satisfied by both UCAS and LCAS.
22. tCPN and tCP are determined by the time that both UCAS and LCAS are high.
23. When output buffers are enabled once, sustain the low impedance state until valid data is
obtained. When output buffer is turned on and off within a very short time, generally it causes
large VCC/VSS line noise, which causes to degrade VIH min/VIL max level.
24. tCRP is planned to be improved to match the standard DRAM specifications.
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| Páginas | Total 22 Páginas | |
| PDF Descargar | [ Datasheet HM514280A.PDF ] | |
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