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CD4519B PDF даташит

Спецификация CD4519B изготовлена ​​​​«Harris Semiconductor» и имеет функцию, называемую «CD4000B Series».

Детали детали

Номер произв CD4519B
Описание CD4000B Series
Производители Harris Semiconductor
логотип Harris Semiconductor логотип 

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CD4519B Даташит, Описание, Даташиты
Technical Overview
CD4000B Series
This section is intended as a guide for circuit and equipment
designers in the operation and application of MOS inte-
grated circuits. It covers general operating and handling con-
siderations with respect to the following critical factors:
• Operating Supply Voltage Range
• Power Dissipation and Derating
• System Noise Considerations
• Power Source Rules
• Gate-oxide Protection Networks
• Input Signals and Ratings
www.DataSheet4U.Ccohmip Assembly and Storage
• Device Mounting
• Testing
More specific information is then given on significant fea-
tures, special design and application requirements, and
standard ratings and electrical characteristics for CMOS B-
series logic circuits, and on CMOS special function circuits
(special interface and display driver circuits).
General Operating and Handling
Considerations
The following paragraphs discuss some key operating and
handling considerations that must be taken into account to
achieve maximum advantage of the CMOS technology.
Additional information on the operation and handling of
CMOS integrated circuits is given in Application Note
AN6525, “Guide to Better Handling and Operation of CMOS
Integrated Circuits”. See Section 8, “How to Use Answer-
FAX”, in this selection guide.
Operating Supply Voltage Range
Because logic systems occasionally experience transient con-
ditions on the power supply line which, when added to the
nominal power-bus voltage, could exceed the safe limits of cir-
cuits connected to the power bus, the recommended operat-
ing supply voltage range is 3V to 18V for B-series devices.
The recommended maximum power supply limit is substan-
tially below the minimum primary breakdown limit for the
devices to allow for limited power supply transient and regula-
tion limits. For circuits that operated in a linear mode over a
portion of the voltage range, such as RC or crystal oscillators,
a minimum supply voltage of 4V is recommended.
Power Dissipation and Derating
The power dissipation of a CMOS integrated circuit is the
sum of a DC (quiescent) component and an AC (dynamic)
components. The DC component is the sum of the net inte-
grated circuit reverse diode junction current and the surface
leakage current times the supply voltage. In standard B-
series logic devices, the DC dissipation typically ranges,
depending upon device complexity, from 100nW to 400nW
for a supply voltage of 10V. Worst-case DC dissipation is the
product of the maximum quiescent current (given in the data
sheet on each device) and the DC supply voltage VDD.
Dynamic power dissipation has three components:
1. The dissipation that results from current that charges and
discharges the external load capacitance of the output
buffers. The dissipation of each output buffer is equal to
CV2f, where C is the load capacitance, V is the supply
voltage, and f is the switching frequency of that output.
2. The dissipation that results from current that charges and
discharges the internal node capacitances.
3. The dissipation caused by the current spikes through the
PMOS and NMOS transistors in series at the instant of
switching. This component amounts to approximately
10% of the total dissipation, shown graphically in the
datasheets of most CMOS circuits.
All CMOS devices are rated at 200mW per package at the
maximum operating ambient temperature rating (TA) of
125oC for all packages. Power ratings for temperatures
below the maximum operating temperature are shown in the
standard CMOS thermal derating chart in Figure 1. This
chart assumes that the device is mounted and soldered (or
placed in a socket) on a PC board; there is natural convec-
tion cooling, with the PC board mounted horizontally; and
the pressure is standard (14.7psia). In addition to the overall
package dissipation, device dissipation per output transistor
is limited to 100mW maximum over the full package operat-
ing temperature range.
SLOPE = 12mW/oC
600
500
400
300
200
100
20 40 60 80 85 100
TA, AMBIENT TEMPERATURE (oC)
120 125
FIGURE 1. STANDARD CMOS THERMAL DERATING CHART
System Noise Considerations
In general, CMOS devices are much less sensitive to noise
on power and ground lines than bipolar logic families (such
as TTL or DTL). However, this sensitivity varies as a function
of the power supply voltage, and more importantly as a func-
tion of synchronism between noise spikes and input transi-
tions. Good power distribution in digital systems requires
that the power bus have a low dynamic impedance; for this
purpose, discrete decoupling capacitors should be distrib-
uted across the power bus. A more detailed discussion of
CMOS noise immunity is provided by Application Note
AN6587, “Noise Immunity of B-series CMOS Integrated Cir-
cuits”. See Section 8, “How to Use AnswerFAX”, in this
selection guide.
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CD4519B Даташит, Описание, Даташиты
Technical Overview
Power Source Rules
Figure 2 shows the basic CMOS inverter and its gate-oxide
protection network plus inherent diodes. The safe operating
procedures listed below can be understood by reference to
this inverter.
VDD
(NOTE 1)
D2
D2 D2
D1
IN
R1
COS/MOS
R2
D1
D1 (NOTE 1) D1
D1
OUT
and/or P-N junctions. Figure 3 shows the gate-oxide protec-
tion circuits used to protect CMOS devices from static elec-
tricity damage. Application Note AN6525, “Guide to Better
Handling and Operation of CMOS Integrated Circuits”. See
Section 8, “How to Use AnswerFAX”, in this selection guide.
VDD
IN (NOTE 1)
(NOTE 1)
OUT
VSS
www.DataSheet4NUO.cToEmS:
1. These Diodes are inherently part of the manufacturing process.
2. Diode Breakdown
D1 25V
D2 50V
R2 << R1
FIGURE 2. BASIC CMOS INVERTER WITH B-SERIES TYPE
PROTECTION NETWORK
1. When separate power supplies are used for the CMOS
device and for the device inputs, the device power supply
should always be turned on before the independent input
signal sources, and the input signals should be turned off
before the power supply is turned off (VSS VI VDD as
a maximum limit). This rule will prevent over dissipation
and possible damage to the D2 input protection diode
when the device power supply is grounded. When the de-
vice power supply is an open circuit, violation of this rule
can result in undesired circuit operation although device
damage should not result: AC inputs can be rectified by
diode D2 to act as a power supply.
2. The power supply operating voltage should be kept safely
below the absolute maximum supply rating, as indicated
previously.
3. The power supply polarity for CMOS circuits should not be
reversed. The positive (VDD) terminal should never be
more than 0.5V negative with respect to the negative
(VSS) terminal (VDD - VSS > -0.5V). Reversal of polarities
will forward-bias and short the structural and protection
diode between VDD and VSS.
4. VDD should be equal to or greater than VCC for CMOS
buffers which have two power supplies (except for the
CD40109B, and in particular, for CD4009 and CD4010
CMOS-to-TTL “down” conversion devices).
5. Power source current capability should be limited to as
low a value as reasonable to assure good logic operation.
6. Large values of resistors in series with VDD or VSS should
be avoided; transient turn-on of input protection diodes
can result from drops across such resistors during
switching.
Gate-Oxide Protection Network
A problem occasionally encountered in handling and testing
low power semiconductor devices, including MOS and small
geometry bipolar devices, has been damage to gate oxide
VSS
FIGURE 3A. FOR B-SERIES CMOS PRODUCT
VDD (NOTE 2)
CD4049UB
IN (NOTE 1)
(NOTE 1)
OUT
CD4050B
CD40109B
VSS
FIGURE 3B. FOR CD4049UB AND CD4050B AND CD40109B
CMOS TYPES
GATE 1
IN /OUT
D1 (NOTE 1)
N-SUB
VDD (NOTE 1) D1
D2 (NOTE 1)
VSS
P-WELL
(NOTE 1) D2
OUT/ IN
GATE 2
FIGURE 3C. FOR CMOS TRANSMISSION GATES
NOTES:
1. These Diodes are inherently part of the manufacturing process.
2. VCC for CD4049UB and CD4050B
3. Diode Breakdown
D1 25V
D2 50V
FIGURE 3. GATE-OXIDE PROTECTION NETWORKS USED IN
HARRIS CMOS INTEGRATED CIRCUITS
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CD4519B Даташит, Описание, Даташиты
Technical Overview
Input Signals and Ratings
Input signals should be maintained with in the power supply
voltage range, VSS VI VDD. If the input signal exceeds the
recommended input signal swing range, the input current
should be limited to ±100µA to minimize cross talk between
input signals on adjacent terminals, and also to minimize any
reduction in noise immunity.
The absolute maximum input current rating of ±10mA, shown
in the published data, protects the device against the possible
occurrence of an induced VDD - VSS latch condition, or dam-
age to the input protection diodes. Latch-up conditions are
explained in Application Note AN6525, “Guide to Better Han-
dling and Operation of CMOS Integrated Circuits”. See Sec-
tion 8, “How to Use AnswerFAX”, in this selection guide.
www.DataSheet4AUL.cLomCMOS inputs should be terminated. An exception can
be made in the case of unbuffered NOR and NAND gates
where terminating one of the series inputs to the proper
polarity will not permit current flow caused by a floating
input. Thus tying low one of the inputs of an unbuffered
NAND gate, or tying high one of the inputs of an unbuffered
NOR gate will satisfy this requirement.
When CMOS inputs are wired to edge card connectors with
CMOS drive coming from another PC board, a shunt resistor
in the range of 100kW should be connected to VDD or VSS,
as applicable, in case the inputs become unterminated with
the power supply on.
When CMOS circuits are driven by TTL logic, a “pull-up”
resistor should be connected from the CMOS input to 5V
(further information is given in Application Note AN6602,
“Interfacing COS/MOS with Other Logic Families”, See Sec-
tion 8, “How to Use AnswerFAX”, in this selection guide.
Output Rules
1. The power dissipation in a CMOS package should not ex-
ceed the rated value for the ambient temperature speci-
fied. The actual dissipation should be calculated when
shorting outputs directly to VDD or VSS, driving low im-
pedance loads, or directly driving the base of P-N-P or
N-P-N bipolar transistor.
2. Output short circuits often result from testing errors or im-
proper board assembly. Shorts on buffer outputs or
across power supplies greater than 5V can damage
CMOS devices.
3. CMOS, like active pull-up TTL, can be connected in the
“wire-OR” configuration because an “on” PMOS and an
“on” NMOS transistor could be directly shorted across the
power supply rails. (Exception: CD40107B)
7. Output transistors may be over dissipated by operating
buffers as linear amplifiers or using these types as one
shot or astable multivibrators.
Noise immunity and Noise Margin
The complementary structure of the inverter, common to all
CMOS logic devices, results in a near-ideal input-output
transfer characteristic, with switching point midway (45% to
55%) between the 0 and 1 output logic levels. The result is
high DC noise immunity.
Figure 4 shows a typical transfer curve that may be used to
define the DC noise immunity of CMOS integrated circuits.
The noise immunity voltage (VIL or VIH) is the noise voltage
at any one input that does not propagate through the sys-
tem. Minimum noise immunity for buffered B-series CMOS
devices is 30%, 30%, and 27%, respectively for supply volt-
ages VDD of 5V, 10V, 15V and 20% of VDD for all unbuffered
gates. The VIL and VIH specifications define the maximum
permissible additive noise voltage at an input terminal when
input signals are within 50mV of the supply rails.
VO(HIGH)
VOUT
VO(LOW)
10
9
8
7
6
5
4
3
2
1
VIL (TYP)
VNML = VIL (MAX) - VO(LOW)
VNML = VO(HIGH) - VIH (MIN)
VIH TYP
0 1 2 3 4 5 6 7 8 9 10
VIL MAX
VIN VIH MIN
FIGURE 4. TYPICAL TRANSFER CURVE FOR A INVERTING
GATE AT VDD = 10V
Noise margin is the difference between the noise-immunity
voltage (VIL or VIH) and the output voltage VO. Noise margin
voltage is the maximum voltage that can be impressed upon
an input voltage VIN (where VIN is the VOL or VOH voltage of
the preceding stage) at any (or all) logic I/O terminals with-
out upsetting the logic or causing any output to exceed the
output voltage (VO) conditions specified for VIL and VIH rat-
ings. Figure 5 illustrates the noise margin concept in a sim-
ple system. Minimum noise margins for buffered B-series
CMOS devices are 1V, 2V, and 2.5V, respectively, for supply
voltages 5V, 10V, and 15V.
4. Paralleling inputs and outputs of gates is recommended
only when the gates are within the same IC package.
5. Output loads should return to a voltage within the supply
voltage range VDD to VSS.
6. Large capacitive loads (greater than 5000pF) on CMOS
buffers or high current drivers act like short circuits and
may over dissipate output transistors.
VDD = 5V
VIH = 3.5V
VOL = 0.5V
VNML = 1V
VIL = 1.5V
VOH = 4.5V
VNML = 1V
VIH = 3.5V
VOL = 0.5V
FIGURE 5. NOISE MARGIN EXAMPLE USING INVERTERS
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[ CD4519B.PDF Даташит ]

Номер в каталогеОписаниеПроизводители
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ETC
CD4519BCD4000B SeriesHarris Semiconductor
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