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PDF HFDOM44MVxxx Data sheet ( Hoja de datos )
| Número de pieza | HFDOM44MVxxx | |
| Descripción | 44Pin Disk On Module | |
| Fabricantes | Hanbit Electronics | |
| Logotipo |  |
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HANBit
HFDOM44MVxxx
44Pin Disk On Module Min.16MB ~ Max.1.5GB, True IDE Interface
Mode, 3.3V / 5.0V Operating
Part No. HFDOM44MVxxx
1. PRODUCT OVERVIEW
GENERAL DESCRIPTION
The HFDOM44MVxxx series 44Pin Flash Disk Module is a flash technology based with True IDE interface flash memory
card. It is constructed with flash disk controller chip and NAND-type (Samsung) flash memory device. The HFDOM44MV-
xxx series operates in both 3.3-Volt and 5.0-Volt power supplies. It comes in capacity of 16, 32, 64, 96, 128, 192, 256, 384,
512, 768, 1Gand up to 1.5GB formatted 44Pin type .
www.DataSheet4UB.ycoomptimizing flash memory management, the life of this HFDOM44MVxxx series can be extended to its maximum level.
Because the ECC function is included, the correctness of data transfer between the HFDOM44MVxxx series and a True
IDE compatible interface device can be guaranteed.
The HFDOM44MVxxx series is fully compatible with applications such as CPU card / board, set top box, industry /
military PC / Notebook, security equipment, measuring instrument and embedded systems.
FEATURES
- ATA / True IDE compatible host interface
- ATA command set compatible
- Automatic sensing of PC Card ATA or true IDE host interface.
- Very high performance, low power consumption
- Automatic error detection and error correction
- Auto Standby to save power consumption.
- Supports automatic power down and wake up
- Support for 8 or 16 bit host transfers
- 3.3V/5.0V operation voltage
- Host Interface bus width : 8/16 bit Access
- Flash Interface bus width : 8 bit Access
- Capacity : Min. 16MB ~ Max. 1.5GB
PRODUCT SPECIFICATIONS
Capacities :
16, 32, 64, 96, 128, 192, 256, 384, 512, 768, 1Gand up to 1.5GB (formatted)
System Compatibility :
Please refer to the compatibility list of index.
Performance :
Host Data Transfer Rates :
up to 16.6 MB/sec, PIO mode 4; 16.6MB/sec, Multi-word
DMA mode 2; 33MB/sec
URL:www.hbe.co.kr
Rev. 1.0 (July. 2004)
1 / 13
HANBit Electronics Co., Ltd.
1 page  
HANBit
HFDOM44MVxxx
Signal Descriptions
Table 2.2 Signal Descriptions
Signal Name Dir.
Pin
Description
A[2:0]
-PDIAG
-DASP
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-CS0, -CS1
D[15:00]
GND
-IOR
-IOW
IRQ
-RESET
In True IDE Mode only A[2:0] are used to select the one of eight registers in
I 33,35,36 the Task File, the remaining address lines should be grounded by the host.
This input / output is the Pass Diagnostic signal in the Master / Slave
I/O 34 handshake protocol.
In the True IDE Mode, this input/output is the Disk Active/Slave
I/O 39 Present signal in the Master/Slave handshake protocol.
CS0 is the chip select for the task file registers while CS2 is used to select
I 37,38 the Alternate Status Register and the Device Control Register.
3,4,5,6,
All Task File operations occur in byte mode on the low order bus D00-D07
while all data transfers are 16 bit using D00-D15.
7,8,9,10,
I/O 11,12,13,
14,15,16,
17,18
2,19,22, Ground.
-- 24,26,
30,40,
I 25 This is an I/O Read strobe generated by the host.
The I/O Write strobe pulse is used to clock I/O data on the Card Data bus
into the Storage Card controller registers when the Storage Card is
I 23 configured to use the I/O interface. The clocking will occur on the negative to
positive edge of the signal (trailing edge).
O 31 In True IDE Mode signal is the active high Interrupt Request to the host.
I 1 This input pin is the active low hardware reset from the host.
IORDY
-IOIS16
O 27 This output signal may be used as IORDY.
This output signal is asserted low when this device is expecting a word data
O 32 transfer cycle.
URL:www.hbe.co.kr
Rev. 1.0 (July. 2004)
5 / 13
HANBit Electronics Co., Ltd.
5 Page 
HANBit
HFDOM44MVxxx
Card Address Register
This register is provided for compatibility with the AT disk drive interface. It is recommended that this
register not be mapped into the host’s I/O space because of potential conflicts on Bit 7. The bits are defined
as follows:
D7 D6 D5 D4 D3 D2 D1 D0
X
-WTG
-HS3
-HS2
-HS1
-HS0
-nDS1
-nDS0
Bit 7: This bit is reserved.
Implementation Note:
Conflicts may occur on the host data bus when this bit is provided by a Floppy Disk Controller
www.DataSheeost4opUleu.rtcaiootminnsgtaottthhies
same addresses as the CompactFlash Storage
problem for the PCMCIA implementation:
Card.
Following
are
some
possible
1) Locate the CompactFlash Storage Card at a non-conflicting address, i.e. Secondary address (377)
or in an independently decoded Address Space when a Floppy Disk Controller is located at the
Primary addresses.
2) Do not install a Floppy and a CompactFlash Storage Card in the system at the same time.
3) Implement a socket adapter which can be programmed to (conditionally) tri-state D7 of I/0 address
3F7h/377h when a CompactFlash Storage Card is installed and conversely to tri-state
D6-D0 of I/O addresses 3F7h/377h when a floppy controller is installed.
4) Do not use the CompactFlash Storage Card’s Drive Address register. This may be accomplished
by either a) If possible, program the host adapter to enable only I/O addresses 1F0h-1F7h, 3F6h (or
170h-177h, 176h) to the CompactFlash Storage Card or b) if provided use an additional Primary /
Secondary configuration in the CompactFlash Storage Card which does not respond to accesses to
I/O locations 3F7h and 377h. With either of these implementations, the host software must not
attempt to use information in the Drive Address Register.
Bit 6 (-WTG): This bit is 0 when a write operation is in progress, otherwise, it is 1.
Bit 5 (-HS3): This bit is the negation of bit 3 in the Drive/Head register.
Bit 4 (-HS2): This bit is the negation of bit 2 in the Drive/Head register.
Bit 3 (-HS1): This bit is the negation of bit 1 in the Drive/Head register.
Bit 2 (-HS0): This bit is the negation of bit 0 in the Drive/Head register.
Bit 1 (-nDS1): This bit is 0 when drive 1 is active and selected.
Bit 0 (-nDS0): This bit is 0 when the drive 0 is active and selected.
Data Register
The Data Register is a 16-bit register, and it is used to transfer data blocks between the CompactFlash
Storage Card data buffer and the Host. This register overlaps the Error Register. The table below describes
the combinations of data register access and is provided to assist in understanding the overlapped Data
Register and Error/Feature Register rather than to attempt to define general PCMCIA word and byte
access modes and operations. See the PCMCIA PC Card Standard Release 2.0 for definitions of the Card
Accessing Modes for I/O and Memory cycles.
15 14 13 12 11 10
Data (15:8)
765432
Data (7:0)
9
1
8
0
Feature Register
This register provides information regarding features of the CompactFlash Storage Card that the
host can utilize. This register is also accessed on data bits D15-D8 during a write operation to
Offset 0 with -CE2 low and -CE1 high.
7 6 5 4 3 2 10
Command specific
URL:www.hbe.co.kr
Rev. 1.0 (July. 2004)
11 / 13
HANBit Electronics Co., Ltd.
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