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Спецификация N82C55AN изготовлена «Integral» и имеет функцию, называемую «IN82C55AN». |
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Детали детали
Номер произв | N82C55AN |
Описание | IN82C55AN |
Производители | Integral |
логотип |
21 Pages
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IN82C55AN
CHMOS PROGRAMMABLE PERIPHERAL INTERFACE
The Integral IN82C55AN is a high-performance, CHMOS version of the industry standard
IN82C55AN general purpose programmable I/O device which is designed for use with all
Intel and most other microprocessors. It provides 24 I/O pins which may be individually
programmed in 2 groups of 12 and used in 3 major modes of operation.
In MODE 0, each group of 12 I/O pins may be programmed in sets of 4 and 8 to be inputs
or outputs. In MODE 1, each group may be programmed to have 8 lines of input or output.
3 of the remaining 4 pins are used for handshaking and interrupt control signals. MODE 2
is a strobed bi-directional bus configuration.
FEATURES
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• Compatible with all Intel and Most Other Microprocessors
• High Speed, «Zero Wait State» Operation with 8MHz 8086/88 and 80186/188
• 24 Programmable I/O Pins
• Low Power CHMOS
• Completely TTL Compatible
• Control Word Read-Back Capability
• Direct Bit Set/Reset Capability
• 2.5mA DC Drive Capability on all I/O Port Outputs
• Available in 40-Pin DIP
• Available in EXPRESS
Standard Temperature Range
Extended Temperature Range
GROUP
A
CONTROL
D7-D0
DATA
BUS
BUFFER
8 BIT
INTERNAL
DATA BUS
RD
WR
A1
A0
Reset
CS
READ/
WRITE
CONTROL
LOGIC
GROUP
B
CONTROL
Figure 1
GROUP
A
PORT
A
(8)
GROUP
A
PORT C
UPPER
(4)
GROUP
B
PORT C
LOWER
(4)
GROUP
B
PORT
B
(8)
PA7-PA0
PC7-PC4
PC3-PC0
PB7-PB0
PA3
PA2
PA1
PA0
RD
CS
VSS
A1
A0
PC7
PC6
PC5
PC4
PC0
PC1
PC2
PC3
PB0
PB1
PB2
1. 40
2. 39
3. 38
4. 37
5. 36
6. 35
7. 34
8. 33
9. 32
10 31
11 30
12 29
13 28
14 27
15 26
16 25
17 24
18 23
19 22
20 21
Figure 2
PA4
PA5
PA6
PA7
WR
Reset
D0
D1
D2
D3
D4
D5
D6
D7
VCC
PB7
PB6
PB5
PB4
PB3
1
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IN82C55AN
Symbol
PA3-0
RD
CS
GND
A1-0
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PC7-4
PC0-3
PB0-7
VCC
D7-0
RESET
WR
PA7-4
Pin
number
1-4
5
6
7
8-9
10-13
14-17
18-25
26
27-34
35
36
37-40
Type
I/O
I
I
I
I/O
I/O
I/O
I/O
I
I
I/O
Name and Function
PORT A, PINS 0-3: Lower nibble of an 8-bit data output latch
buffer and an 8-bit data input latch.
READ CONTROL: This input is low during CPU read
operations.
CHIP SELECT: A low on this input enables the 82C55A to
respond to RD and WR signals RD and WR are ignored
otherwise.
System Ground.
ADDRESS: These input signals in conjunction RD and WR
control the selection of one of the three ports or the control
word registers.
A1 A0 RD WR CS Input Operation (Read)
0 0 0 1 0 Port A - Data Bus
0 1 0 1 0 Port B - Data Bus
1 0 0 1 0 Port C - Data Bus
1 1 0 1 0 Control Word - Data Bus
Output Operation (Write)
0 0 1 0 0 Data Bus - Port A
0 1 1 0 0 Data Bus - Port B
1 0 1 0 0 Data Bus - Port C
1 1 1 0 0 Data Bus – Control
Disable Function
x x x x 1 Data Bus-3-State
x x 1 1 0 Data Bus-3-State
PORT C, PINS 4-7: Upper nibble of an 8-bit data output
latch/buffer and an 8-bit data input buffer (no latch for input).
This port can be divided into two 4-bit ports under the mode
control. Each 4-bit port contains a 4-bit latch and it can be used
for the control signal outputs and status signal inputs in
conjunction with ports A and B.
PORT C, PINS 0-3: Lower nibble of Port C.
PORT B, PINS 0-7: An 8-bit data output latch/buffer and an 8-
bit data input buffer
SYSTEM POWER: +5V Power Supply
DATA BUS: Bi-directional, tri-state data bus lines, connected to
system data bus
RESET: A high on this input clears the control register and all
ports are set to the input mode
WRITE CONTROL: This input is low during CPU write
operations
PORT A PINS 4-7: Upper nibble of an 8-bit data output
latch/buffer and an 8-bit data input latch
2
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IN82C55AN
IN82C55AN FUNCTIONAL DESCRIPTION
General
The IN82C55AN is a programmable peripheral interface device designed for use in Intel microcomputer
systems. Its function is that of a general purpose I/O component to interface peripheral equipment to the
microcomputer system bus. The functional configuration of the IN82C55AN is programmed by the system
software so that normally no external logic is necessary to interface peripheral devices or structures.
Data Bus Buffer
This 3-state bidirectional 8-bit buffer is used to interface the IN82C55AN to the system data bus. Data is
transmitted or received by the buffer upon execution of input or output instructions by the CPU. Control
words and status information are also transferred through the data bus buffer.
Read/Write and Control Logic
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this block is to
accepts inputs
manage all of
from the CPU
the internal and external transfers of both Data and Control
Address and Control busses and in turn, issues commands
or
to
both of the Control Groups.
Group A and Group B Controls
The functional configuration of each port is programmed by the systems software. In essence, the CPU
“outputs” a control word to the IN82C55AN. The control word contains information such as “mode”, “bit set”,
“bit reset”, etc., that initializes the functional configuration of the 82C55A. Each of the Control blocks (Group
A and Group B) accepts “commands” from the Read/Write Control Logic, receives “control words” from the
internal data bus and issues the proper commands to its associated ports.
Control Group A - Port A and Port C upper (C7 - C4)
Control Group B - Port B and Port C lower (C3 - C0)
The control word register can be both written and read as shown in the address decode table in the pin
descriptions. Figure 6 shows the control word format for both Read and Write operations. When the control
word is read, bit D7 will always be a logic “1”, as this implies control word mode information.
Ports A, B, and C
The IN82C55AN contains three 8-bit ports (A, B, and C). All can be configured in a wide variety of functional
characteristics by the system software but each has its own special features or “personality” to further
enhance the power and flexibility of the IN82C55AN.
Port A. One 8-bit data output latch/buffer and one 8-bit input latch/buffer. Both “pull-up” and “pull-down” bus
hold devices are present on Port A.
Port B. One 8-bit data input/output latch/buffer. Only “pull-up” bus hold devices are present on Port B.
Port C. One 8-bit data output latch/buffer and one 8-bit data input buffer (no latch for input). This port can be
divided into two 4-bit ports under the mode control. Each 4-bit port contains a 4-bit latch and it can be used
for the control signal outputs and status signal inputs in conjunction with ports A and B. Only “pull-up” bus
hold devices are present on Port C.
See Figure 4 for the bus-hold circuit configuration for Port A, B, and C.
3
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Номер в каталоге | Описание | Производители |
N82C55A | CHMOS PROGRAMMABLE PERIPHERAL INTERFACE | Intel Corporation |
N82C55AN | IN82C55AN | Integral |
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