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NT5SV16M8CT PDF даташит

Спецификация NT5SV16M8CT изготовлена ​​​​«Nanya Techology» и имеет функцию, называемую «(NT5SVxxMxxCT) 128Mb SDRAM».

Детали детали

Номер произв NT5SV16M8CT
Описание (NT5SVxxMxxCT) 128Mb SDRAM
Производители Nanya Techology
логотип Nanya Techology логотип 

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NT5SV16M8CT Даташит, Описание, Даташиты
NT5SV32M4CT
NT5SV16M8CT
NT5SV8M16CT
128Mb Synchronous DRAM
Features
• High Performance:
fCK
Clock
Frequency
tCK Clock Cycle
tAC
Clock Access
Time1
www.DataSheettA4CU.coCTmilmocek2 Access
-7K 3
CL=2
133
7.5
5.4
-75B,
CL=3
133
7.5
-8B,
CL=2
100
10
Units
MHz
ns
ns
5.4 6 ns
1. Terminated load. See AC Characteristics on page 37.
2. Unterminated load. See AC Characteristics on page 37.
3. tRP = tRCD = 2 CKs
• Single Pulsed RAS Interface
• Fully Synchronous to Positive Clock Edge
• Four Banks controlled by BS0/BS1 (Bank Select)
• Programmable CAS Latency: 2, 3
• Programmable Burst Length: 1, 2, 4, 8
• Programmable Wrap: Sequential or Interleave
• Multiple Burst Read with Single Write Option
• Automatic and Controlled Precharge Command
• Data Mask for Read/Write control (x4, x8)
• Dual Data Mask for byte control (x16)
• Auto Refresh (CBR) and Self Refresh
• Suspend Mode and Power Down Mode
• Standard Power operation
• 4096 refresh cycles/64ms
• Random Column Address every CK (1-N Rule)
• Single 3.3V ± 0.3V Power Supply
• LVTTL compatible
• Package: 54-pin 400 mil TSOP-Type II
Description
The NT5SV32M4CT, NT5SV16M8CT, and NT5SV8M16CT
are four-bank Synchronous DRAMs organized as 8Mbit x 4
I/O x 4 Bank, 4Mbit x 8 I/O x 4 Bank, and 2Mbit x 16 I/O x 4
Bank, respectively. These synchronous devices achieve
high-speed data transfer rates of up to 133MHz by employing
a pipeline chip architecture that synchronizes the output data
to a system clock. The chip is fabricated with NTC’s
advanced 128Mbit single transistor CMOS DRAM process
technology.
The device is designed to comply with all JEDEC standards
set for synchronous DRAM products, both electrically and
mechanically. All of the control, address, and data input/out-
put (I/O or DQ) circuits are synchronized with the positive
edge of an externally supplied clock.
RAS, CAS, WE, and CS are pulsed signals which are exam-
ined at the positive edge of each externally applied clock
(CK). Internal chip operating modes are defined by combina-
tions of these signals and a command decoder initiates the
necessary timings for each operation. A fourteen bit address
bus accepts address data in the conventional RAS/CAS mul-
tiplexing style. Twelve row addresses (A0-A11) and two bank
select addresses (BS0, BS1) are strobed with RAS. Eleven
column addresses (A0-A9, A11) plus bank select addresses
and A10 are strobed with CAS. Column address A11 is
dropped on the x8 device, and column addresses A11 and
A9 are dropped on the x16 device.
Prior to any access operation, the CAS latency, burst length,
and burst sequence must be programmed into the device by
address inputs A0-A11, BS0, BS1 during a mode register set
cycle. In addition, it is possible to program a multiple burst
sequence with single write cycle for write through cache oper-
ation.
Operating the four memory banks in an interleave fashion
allows random access operation to occur at a higher rate
than is possible with standard DRAMs. A sequential and gap-
less data rate of up to 133MHz is possible depending on
burst length, CAS latency, and speed grade of the device.
Auto Refresh (CBR) and Self Refresh operation are sup-
ported.
REV 1.0
May, 2001
1
© NANYA TECHNOLOGY CORP. All rights reserved.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.









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NT5SV16M8CT Даташит, Описание, Даташиты
NT5SV32M4CT
NT5SV16M8CT
NT5SV8M16CT
128Mb Synchronous DRAM
Pin Assignments for Planar Components (Top View)
www.DataSheet4U.com
VD D
DQ0
VDDQ
DQ1
DQ2
VSSQ
DQ3
DQ4
VDDQ
DQ5
DQ6
VSSQ
DQ7
VD D
LDQM
WE
CAS
RAS
CS
BS0
BS1
A10/AP
A0
A1
A2
A3
VDD
VDD
DQ0
VDDQ
NC
DQ1
V SSQ
NC
DQ2
VDDQ
NC
DQ3
VSSQ
NC
VDD
NC
WE
CAS
RAS
CS
BS0
BS1
A10/AP
A0
A1
A2
A3
VDD
V DD
NC
VDDQ
NC
DQ0
VSSQ
NC
NC
VDDQ
NC
DQ1
VSSQ
NC
V DD
NC
WE
CAS
RAS
CS
BS0
BS1
A10/AP
A0
A1
A2
A3
V DD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
54 VSS
53 NC
52 VSSQ
51 NC
50 DQ3
49 VDDQ
48 NC
47 NC
46 VSSQ
45 NC
44 DQ2
43 VDDQ
42 NC
41 VSS
40 NC
39 DQM
38 CK
37 CKE
36 NC
35 A11
34 A9
33 A8
32 A7
31 A6
30 A5
29 A4
28 VSS
V SS
DQ7
V SSQ
NC
DQ6
V DDQ
NC
DQ5
V SSQ
NC
DQ4
V DDQ
NC
V SS
NC
DQM
CK
CKE
NC
A11
A9
A8
A7
A6
A5
A4
V SS
VSS
DQ15
VSSQ
DQ14
DQ13
VDDQ
DQ12
DQ11
VSSQ
DQ10
DQ9
VDDQ
DQ8
VSS
NC
UDQM
CK
CKE
NC
A11
A9
A8
A7
A6
A5
A4
VSS
54-pin Plastic TSOP(II) 400 mil
8Mbit x 4 I/O x 4 Bank
NT5SV32M4CT
4Mbit x 8 I/O x 4 Bank
NT5SV16M8CT
2Mbit x 16 I/O x 4 Bank
NT5SV8M16CT
REV 1.0
May, 2001
2
© NANYA TECHNOLOGY CORP. All rights reserved.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.









No Preview Available !

NT5SV16M8CT Даташит, Описание, Даташиты
NT5SV32M4CT
NT5SV16M8CT
NT5SV8M16CT
128Mb Synchronous DRAM
Pin Description
CK
CKE
CS
RAS
CAS
WE
www.DataSheet4U.com
BS1, BS0
A0 - A11
Clock Input
Clock Enable
Chip Select
Row Address Strobe
Column Address Strobe
Write Enable
Bank Select
Address Inputs
DQ0-DQ15
DQM, LDQM, UDQM
VDD
VSS
VDDQ
V SSQ
NC
Data Input/Output
Data Mask
Power (+3.3V)
Ground
Power for DQs (+3.3V)
Ground for DQs
No Connection
Input/Output Functional Description
Symbol
Type
Polarity
Function
CLK
Input
Positive
Edge The system clock input. All of the SDRAM inputs are sampled on the rising edge of the clock.
CKE
Input Active High Activates the CLK signal when high and deactivates the CLK signal when low. By deactivating the
clock, CKE low initiates the Power Down mode, Suspend mode, or the Self Refresh mode.
CS Input Active Low CS enables the command decoder when low and disables the command decoder when high. When the
command decoder is disabled, new commands are ignored but previous operations continue.
RAS, CAS,
WE
When sampled at the positive rising edge of the clock, CAS , RAS , and WE define the operation to be
Input Active Low
executed by the SDRAM.
BS0, BS1
Input
— Selects which bank is to be active.
A0 - A11
Input
During a Bank Activate command cycle, A0-A11 defines the row address (RA0-RA11) when sampled at
the rising clock edge.
During a Read or Write command cycle, A0-A9 and A11 defines the column address (CA0-CA9, CA11)
when sampled at the rising clock edge.
A10 is used to invoke auto-precharge operation at the end of the burst read or write cycle. If A10 is
high, auto-precharge is selected and BS0, BS1 defines the bank to be precharged. If A10 is low, auto-
precharge is disabled.
During a Precharge command cycle, A10 is used in conjunction with BS0, BS1 to control which bank(s)
to precharge. If A10 is high, all banks will be precharged regardless of the state of BS. If A10 is low,
then BS0 and BS1 are used to define which bank to precharge.
DQ0 - DQ15 Input-
— Data Input/Output pins operate in the same manner as on conventional DRAMs.
Output
DQM
LDQM
UDQM
Input
The Data Input/Output mask places the DQ buffers in a high impedance state when sampled high. In
x16 products, LDQM and UDQM control the lower and upper byte I/O buffers, respectively. In Read
Active High mode, DQM has a latency of two clock cycles and controls the output buffers like an output enable.
DQM low turns the output buffers on and DQM high turns them off. In Write mode, DQM has a latency
of zero and operates as a word mask by allowing input data to be written if it is low but blocks the write
operation if DQM is high.
VD D, VSS
Supply
Power and ground for the input buffers and the core logic.
V DDQ VSSQ Supply — Isolated power supply and ground for the output buffers to provide improved noise immunity.
REV 1.0
May, 2001
3
© NANYA TECHNOLOGY CORP. All rights reserved.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.










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NT5SV16M8CT(NT5SVxxMxxCT) 128Mb SDRAMNanya Techology
Nanya Techology

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