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N80C42 PDF даташит

Спецификация N80C42 изготовлена ​​​​«Intel Corporation» и имеет функцию, называемую «UNIVERSAL PERIPHERAL INTERFACE CHMOS 8-BIT SLAVE MICROCONTROLLER».

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Номер произв N80C42
Описание UNIVERSAL PERIPHERAL INTERFACE CHMOS 8-BIT SLAVE MICROCONTROLLER
Производители Intel Corporation
логотип Intel Corporation логотип 

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N80C42 Даташит, Описание, Даташиты
UPI-C42 UPI-L42
UNIVERSAL PERIPHERAL INTERFACE
CHMOS 8-BIT SLAVE MICROCONTROLLER
Y Pin Software and Architecturally
Compatible with all UPI-41 and UPI-42
Products
Y Low Voltage Operation with the UPI-
L42
Full 3 3V Support
Y Hardware A20 Gate Support
Y Suspend Power Down Mode
Y
www.DataSheet4U.com
Security Bit Code Protection Support
Y 8-Bit CPU plus ROM OTP EPROM RAM
I O Timer Counter and Clock in a
Single Package
Y 4096 x 8 ROM OTP 256 x 8 RAM 8-Bit
Timer Counter 18 Programmable I O
Pins
Y DMA Interrupt or Polled Operation
Supported
Y One 8-Bit Status and Two Data
Registers for Asynchronous Slave-to-
Master Interface
Y Fully Compatible with all Intel and Most
Other Microprocessor Families
Y Interchangeable ROM and OTP EPROM
Versions
Y Expandable I O
Y Sync Mode Available
Y Over 90 Instructions 70% Single Byte
Y Quick Pulse Programming Algorithm
Fast OTP Programming
Y Available in 40-Lead Plastic 44-Lead
Plastic Leaded Chip Carrier and
44-Lead Quad Flat Pack Packages
(See Packaging Spec Order 240800 Package Type P N
and S)
The UPI-C42 is an enhanced CHMOS version of the industry standard Intel UPI-42 family It is fabricated on
Intel’s CHMOS III-E process The UPI-C42 is pin software and architecturally compatible with the NMOS UPI
family The UPI-C42 has all of the same features of the NMOS family plus a larger user programmable memory
array (4K) hardware A20 gate support and lower power consumption inherent to a CHMOS product
The UPI-L42 offers the same functionality and socket compatibility as the UPI-C42 as well as providing low
voltage 3 3V operation
The UPI-C42 is essentially a ‘‘slave’’ microcontroller or a microcontroller with a slave interface included on the
chip Interface registers are included to enable the UPI device to function as a slave peripheral controller in the
MCS Modules and iAPX family as well as other 8- 16- and 32-bit systems
To allow full user flexibility the program memory is available in ROM and One-Time Programmable EPROM
(OTP)
290414 – 1
Figure 1 DIP Pin
Configuration
290414 – 2
Figure 2 PLCC Pin Configuration
290414 – 3
Figure 3 QFP Pin Configuration
Other brands and names are the property of their respective owners
Information in this document is provided in connection with Intel products Intel assumes no liability whatsoever including infringement of any patent or
copyright for sale and use of Intel products except as provided in Intel’s Terms and Conditions of Sale for such products Intel retains the right to make
changes to these specifications at any time without notice Microcomputer Products may have minor variations to this specification known as errata
COPYRIGHT INTEL CORPORATION 1996
December 1995
Order Number 290414-003









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N80C42 Даташит, Описание, Даташиты
UPI-C42 UPI-L42
Table 1 Pin Description
DIP PLCC QFP
Symbol Pin Pin Pin Type
No No No
Name and Function
TEST 0
1
2 18 I TEST INPUTS Input pins which can be directly tested using conditional
TEST 1
39
43
16
branch instructions
FREQUENCY REFERENCE TEST 1 (T1) functions as the event timer
input (under software control) TEST 0 (T0) is a multi-function pin used
during PROM programming and ROM EPROM verification during Sync
Mode to reset the instruction state to S1 and synchronize the internal clock
to PH1
XTAL 1
2
3 19 O OUTPUT Output from the oscillator amplifier
www.DataSheet4U.com XTAL 2
3
4 20 I INPUT Input to the oscillator amplifier and internal clock generator
circuits
RESET
4
5 22 I RESET Input used to reset status flip-flops set the program counter to
zero and force the UPI-C42 from the suspend power down mode
RESET is also used during EPROM programming and verification
SS 5 6 23 I SINGLE STEP Single step input used in conjunction with the SYNC output
to step the program through each instruction (EPROM) This should be tied
to a5V when not used This pin is also used to put the device in Sync
Mode by applying 12 5V to it
CS 6 7 24 I CHIP SELECT Chip select input used to select one UPI microcomputer
out of several connected to a common data bus
EA 7 8 25 I EXTERNAL ACCESS External access input which allows emulation
testing and ROM EPROM verification This pin should be tied low if
unused
RD 8 9 26 I READ I O read input which enables the master CPU to read data and
status words from the OUTPUT DATA BUS BUFFER or status register
A0 9 10 27 I COMMAND DATA SELECT Address Input used by the master processor
to indicate whether byte transfer is data (A0 e 0 F1 is reset) or command
(A0 e 1 F1 is set) A0 e 0 during program and verify operations
WR 10 11 28 I WRITE I O write input which enables the master CPU to write data and
command words to the UPI INPUT DATA BUS BUFFER
SYNC
11 13 29 O OUTPUT CLOCK Output signal which occurs once per UPI instruction
cycle SYNC can be used as a strobe for external circuitry it is also used to
synchronize single step operation
D0 – D7
(BUS)
12– 19 14– 21 30– 37 I O DATA BUS Three-state bidirectional DATA BUS BUFFER lines used to
interface the UPI microcomputer to an 8-bit master system data bus
P10 – P17 27 – 34 30 – 33 2 – 10
35– 38
I O PORT 1 8-bit PORT 1 quasi-bidirectional I O lines P10 – P17 access the
signature row and security bit
2









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N80C42 Даташит, Описание, Даташиты
UPI-C42 UPI-L42
Table 1 Pin Description (Continued)
DIP PLCC
Symbol Pin
Pin
No No
QFP
Pin
No
Type
Name and Function
P20 – P27 21 – 24 24 – 27 39 – 42
I O PORT 2 8-bit PORT 2 quasi-bidirectional I O lines The lower 4 bits
35– 38 39– 42 11 13– 15
(P20 – P23) interface directly to the 8243 I O expander device and
contain address and data information during PORT 4 – 7 access P21
can be programmed to provide hardware A20 gate support The upper
4 bits (P24 – P27) can be programmed to provide interrupt Request and
DMA Handshake capability Software control can configure P24 as
Output Buffer Full (OBF) interrupt P25 as Input Buffer Full (IBF)
interrupt P26 as DMA Request (DRQ) and P27 as DMA ACKnowledge
(DACK)
www.DataSheet4U.com PROG 25 28
43 I O PROGRAM Multifunction pin used as the program pulse input during
PROM programming
During I O expander access the PROG pin acts as an address data
strobe to the 8243 This pin should be tied high if unused
VCC
40 44
17
VDD
26 29
1
POWER a5V main power supply pin
POWER a5V during normal operation a12 75V during programming
operation Low power standby supply pin
VSS
20 22
38
GROUND Circuit ground potential
Figure 4 Block Diagram
290414 – 4
3










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Номер в каталогеОписаниеПроизводители
N80C42UNIVERSAL PERIPHERAL INTERFACE CHMOS 8-BIT SLAVE MICROCONTROLLERIntel Corporation
Intel Corporation

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