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W29C102 PDF даташит

Спецификация W29C102 изготовлена ​​​​«Winbond» и имеет функцию, называемую «64K 16 CMOS FLASH MEMORY».

Детали детали

Номер произв W29C102
Описание 64K 16 CMOS FLASH MEMORY
Производители Winbond
логотип Winbond логотип 

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W29C102 Даташит, Описание, Даташиты
W29C102
64K × 16 CMOS FLASH MEMORY
GENERAL DESCRIPTION
The W29C102 is a 1-megabit, 5-volt only CMOS flash memory organized as 64K × 16 bits. The
device can be programmed and erased in-system with a standard 5V power supply. A 12-volt VPP is
not required. The unique cell architecture of the W29C102 results in fast program/erase operations
www.DataSheet4U.comwith extremely low current consumption (compared to other comparable 5-volt flash memory
products). The device can also be programmed and erased using standard EPROM programmers.
FEATURES
Single 5-volt program and erase operations
Fast page-write operations
128 words per page
Page program cycle: 10 mS (max.)
Effective word-program cycle time: 39 µS
Optional software-protected data write
Fast chip-erase operation: 50 mS
Read access time: 70/90/120 nS
Typical page program/erase cycles: 1K/10K
Ten-year data retention
Software and hardware data protection
Low power consumption
Active current: 25 mA (typ.)
Standby current: 20 µA (typ.)
Automatic program timing with internal VPP
generation
End of program detection
Toggle bit
Data polling
Latched address and data
TTL compatible I/O
JEDEC standard word-wide pinouts
Available packages: 40-pin 600 mil DIP, TSOP
and 44-pin PLCC
Publication Release Date: March 1998
- 1 - Revision A3









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W29C102 Даташит, Описание, Даташиты
PIN CONFIGURATIONS
www.DataSheet4U.com
NC 1
CE 2
DQ15
3
DQ14
4
DQ13
5
DQ12
6
DQ11
7
DQ10
8
DQ9
9
40-pin
DQ8
GND
10
11
DIP
DQ7
12
DQ6
13
DQ5
14
DQ4
15
DQ3
16
DQ2
17
DQ1
18
DQ0
19
OE 20
40 VDD
39 WE
38 NC
37 A15
36 A14
35 A13
34 A12
33 A11
32 A10
31 A9
30 GND
29 A8
28 A7
27 A6
26 A5
25 A4
24 A3
23 A2
22 A1
21 A0
A9
A10
A11
A12
A13
A14
A15
NC
WE
VDD
NC
CE
DQ15
DQ14
DQ13
DQ12
DQ11
DQ10
DQ9
DQ8
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40-pin
TSOP
40 GND
39 A8
38 A7
37 A6
36 A5
35 A4
34 A3
33 A2
32 A1
31 A0
30 OE
29 DQ0
28 DQ1
27 DQ2
26 DQ3
25 DQ4
24 DQ5
23 DQ6
22 DQ7
21 GND
DDD/
V/
AA
Q Q Q C N N D WN 1 1
13 14 15 E C C D E C 5 4
DQ12
DQ11
DQ10
DQ9
DQ8
GND
NC
DQ7
DQ6
DQ5
DQ4
6 5 4 3 2 1 44 43 42 41 40
7 39
8 38
9 37
10 36
11 44-pin 35
12
PLCC
34
13 33
14 32
15 31
16 30
17 29
18 19 20 21 22 23 24 25 26 27 28
A13
A12
A11
A10
A9
GND
NC
A8
A7
A6
A5
D DDD / N A A A A A
Q QQ Q O C 0 1 2 3 4
3 21 0 E
W29C102
BLOCK DIAGRAM
V DD
VSS
CE
OE
WE
CONTROL
OUTPUT
BUFFER
DQ0
.
.
DQ15
A0
. DECODER
.
A15
CORE
ARRAY
PIN DESCRIPTION
SYMBOL
PIN NAME
A0A15
DQ0DQ15
CE
OE
WE
VDD
GND
NC
Address Inputs
Data Inputs/Outputs
Chip Enable
Output Enable
Write Enable
Power Supply
Ground
No Connection
-2-









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W29C102 Даташит, Описание, Даташиты
W29C102
FUNCTIONAL DESCRIPTION
Read Mode
The read operation of the W29C102 is controlled by CE and OE, both of which have to be low for
the host to obtain data from the outputs. CE is used for device selection. When CE is high, the chip
is de-selected and only standby power will be consumed. OE is the output control and is used to gate
data from the output pins. The data bus is in high impedance state when either CE or OE is high.
www.DataSheet4U.comRefer to the timing waveforms for further details.
Page Write Mode
The W29C102 is programmed on a page basis. Every page contains 128 words of data. If a word of
data within a page is to be changed, data for the entire page must be loaded into the device. Any
word that is not loaded will be erased to "FFh" during programming of the page.
The write operation is initiated by forcing CE and WE low and OE high. The write procedure consists
of two steps. Step 1 is the word-load cycle, in which the host writes to the page buffer of the device.
Step 2 is an internal programming cycle, during which the data in the page buffers are simultaneously
written into the memory array for non-volatile storage.
During the word-load cycle, the addresses are latched by the falling edge of either CE or WE,
whichever occurs last. The data are latched by the rising edge of either CE or WE, whichever occurs
first. If the host loads a second word into the page buffer within a word-load cycle time (TBLC) of 200
µS, after the initial word-load cycle, the W29C102 will stay in the page load cycle. Additional words
can then be loaded consecutively. The page load cycle will be terminated and the internal
programming cycle will start if no additional word is loaded into the page buffer. A7 to A15 specify the
page address. All words that are loaded into the page buffer must have the same page address. A0 to
A6 specify the word address within the page. The words may be loaded in any order; sequential
loading is not required.
In the internal programming cycle, all data in the page buffers, i.e., 128 words of data, are written
simultaneously into the memory array. The typical programming time is 5 mS. The entire memory
array can be written in 2.6 seconds. Before the completion of the internal programming cycle, the host
is free to perform other tasks such as fetching data from other locations in the system to prepare to
write the next page.
Software-protected Data Write
The device provides a JEDEC-approved optional software-protected data write. Once this scheme is
enabled, any write operation requires a series of three-word program commands (with specific data to
a specific address) to be performed before the data load operation. The three-word load command
sequence begins the page load cycle, without which the write operation will not be activated. This
write scheme provides optimal protection against inadvertent write cycles, such as cycles triggered by
noise during system power-up and power-down.
The W29C102 is shipped with the software data protection enabled. To enable the software data
protection scheme, perform the three-word command cycle at the beginning of a page load cycle. The
device will then enter the software data protection mode, and any subsequent write operation must be
preceded by the three-word program command cycle. Once enabled, the software data protection will
remain enabled unless the disable commands are issued. A power transition will not reset the
Publication Release Date: March 1998
- 3 - Revision A3










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