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WCSN0436V1P PDF даташит

Спецификация WCSN0436V1P изготовлена ​​​​«Weida Semiconductor» и имеет функцию, называемую «128Kx36 Pipelined SRAM».

Детали детали

Номер произв WCSN0436V1P
Описание 128Kx36 Pipelined SRAM
Производители Weida Semiconductor
логотип Weida Semiconductor логотип 

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WCSN0436V1P Даташит, Описание, Даташиты
Y7C1350B
WCSN0436V1P
Features
128Kx36 Pipelined SRAM with NoBL™ Architecture
Functional Description
• Pin compatible and functionally equivalent to ZBT™
devices IDT71V546, MT55L128L36P, and MCM63Z736
• Supports 166-MHz bus operations with zero wait states
— Data is transferred on every clock
• Internally self-timed output buffer control to eliminate
the need to use OE
• Fully registered (inputs and outputs) for pipelined
operation
www.DataSheetB4Uy.tceomWrite capability
• 128K x 36 common I/O architecture
• Single 3.3V power supply
• Fast clock-to-output times
— 3.5 ns (for 166-MHz device)
— 3.8 ns (for 150-MHz device)
— 4.0 ns (for 143-MHz device)
— 4.2 ns (for 133-MHz device)
— 5.0 ns (for 100-MHz device)
— 7.0 ns (for 80-MHz device)
• Clock Enable (CEN) pin to suspend operation
• Synchronous self-timed writes
• Asynchronous output enable
• JEDEC-standard 100 TQFP package
• Burst Capability—linear or interleaved burst order
• Low standby power (17.325 mW max.)
Logic Block Diagram
CLK
ADV/LD
A[16:0] 17
CEN
CE1
CE2
CE3
WE
BWS[3:0]
MODE
CONTROL
and WRITE
LOGIC
17
The WCSN0436V1P is a 3.3V, 128K by 36 synchronous-pipe-
lined Burst SRAM designed specifically to support unlimited
true back-to-back Read/Write operations without the insertion
of wait states. The WCSN0436V1P is equipped with the ad-
vanced No Bus Latency™ (NoBL™) logic required to enable
consecutive Read/Write operations with data being trans-
ferred on every clock cycle. This feature dramatically improves
the throughput of the SRAM, especially in systems that require
frequent Write/Read transitions.The WCSN0436V1P is
pin/functionally compatible to ZBT SRAMsIDT71V546,
MT55L128L36P, and MCM63Z736.
All synchronous inputs pass through input registers controlled
by the rising edge of the clock. All data outputs pass through
output registers controlled by the rising edge of the clock. The
clock input is qualified by the Clock Enable (CEN) signal,
which when deasserted suspends operation and extends the
previous clock cycle. Maximum access delay from the clock
rise is 3.5 ns (166-MHz device).
Write operations are controlled by the four Byte Write Select
(BWS[3:0]) and a Write Enable (WE) input. All writes are con-
ducted with on-chip synchronous self-timed write circuitry.
Three synchronous Chip Enables (CE1, CE2, CE3) and an
asynchronous Output Enable (OE) provide for easy bank se-
lection and output three-state control. In order to avoid bus
contention, the output drivers are synchronously three-stated
during the data portion of a write sequence.
CE
DaDta-In
Q
REG.
36
36
128Kx36
MEMORY
ARRAY
36
36
DQ[31:0]
DP[3:0]
OE
Selection Guide
.
Maximum Access Time (ns)
Maximum Operating Current (mA)
Maximum CMOS Standby Current (mA)
.
.
Commercial
Commercial
-166
3.5
400
5
-150
3.8
375
5
-143
4.0
350
5
-133
4.2
300
5
-100
5.0
250
5
-80
7.0
200
5
Document#: 38-05246
Revised Jan 06,2002









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WCSN0436V1P Даташит, Описание, Даташиты
Pin Configuration
www.DataSheet4U.com
DP2
DQ16
DQ17
VDDQ
VSS
DQ18
DQ19
DQ20
DQ21
VSS
VDDQ
DQ22
DQ23
VDDQ
VDD
VDD
VSS
DQ24
DQ25
VDDQ
VSS
DQ26
DQ27
DQ28
DQ29
VSS
VDDQ
DQ30
DQ31
DP3
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
100-Pin TQFP
WCSN0436V1P
WCSN0436V1P
80 DP1
79 DQ15
78 DQ14
77 VDDQ
76 VSS
75 DQ13
74 DQ12
73 DQ11
72 DQ10
71 VSS
70 VDDQ
69 DQ9
68 DQ8
67 VSS
66 VDD
65 VDD
64 VSS
63 DQ7
62 DQ6
61 VDDQ
60 VSS
59 DQ5
58 DQ4
57 DQ3
56 DQ2
55 VSS
54 VDDQ
53 DQ1
52 DQ0
51 DP0
Document #: 38-05246 Rev. **
Page 2 of 14









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WCSN0436V1P Даташит, Описание, Даташиты
WCSN0436V1P
Pin Definitions
Pin Number
50–44,
81–82, 99,
100, 32–37
96–93
Name
A[16:0]
BWS[3:0]
88
www.DataShe8e5t4U.com
WE
ADV/LD
89 CLK
98 CE1
97 CE2
92 CE3
86 OE
87 CEN
29–28,
25–22,
19–18,
13–12, 9–6,
3–2, 79–78,
75–72,
69–68, 63–62
59–56, 53–52
DQ[31:0]
30, 1, 80 51 DP[3:0]
31 MODE
15, 16, 41, 65,
66, 91
4, 11, 14, 20,
27, 54, 61, 70,
77
VDD
VDDQ
I/O
Input-
Synchronous
Input-
Synchronous
Input-
Synchronous
Input-
Synchronous
Input-Clock
Input-
Synchronous
Input-
Synchronous
Input-
Synchronous
Input-
Asynchronous
Input-
Synchronous
I/O-
Synchronous
I/O-
Synchronous
Input Strap pin
Power Supply
I/O Power
Supply
Description
Address Inputs used to select one of the 131,072 address locations. Sampled at
the rising edge of the CLK.
Byte Write Select Inputs, active LOW. Qualified with WE to conduct writes to the
SRAM. Sampled on the rising edge of CLK. BWS0 controls DQ[7:0] and DP0, BWS1
controls DQ[15:8] and DP1, BWS2 controls DQ[23:16] and DP2, BWS3 controls
DQ[31:24] and DP3. See Write Cycle Description table for details.
Write Enable Input, active LOW. Sampled on the rising edge of CLK if CEN is active
LOW. This signal must be asserted LOW to initiate a write sequence.
Advance/Load Input used to advance the on-chip address counter or load a new
address. When HIGH (and CEN is asserted LOW) the internal burst counter is
advanced. When LOW, a new address can be loaded into the device for an access.
After being deselected, ADV/LD should be driven LOW in order to load a new
address.
Clock Input. Used to capture all synchronous inputs to the device. CLK is qualified
with CEN. CLK is only recognized if CEN is active LOW.
Chip Enable 1 Input, active LOW. Sampled on the rising edge of CLK. Used in
conjunction with CE2, and CE3 to select/deselect the device.
Chip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK. Used in
conjunction with CE1 and CE3 to select/deselect the device.
Chip Enable 3 Input, active LOW. Sampled on the rising edge of CLK. Used in
conjunction with CE1 and CE2 to select/deselect the device.
Output Enable, active LOW. Combined with the synchronous logic block inside the
device to control the direction of the I/O pins. When LOW, the I/O pins are allowed
to behave as outputs. When deasserted HIGH, I/O pins are three-stated, and act
as input data pins. OE is masked during the data portion of a write sequence, during
the first clock when emerging from a deselected state, when the device has been
deselected.
Clock Enable Input, active LOW. When asserted LOW the clock signal is recog-
nized by the SRAM. When deasserted HIGH the Clock signal is masked. Since
deasserting CEN does not deselect the device, CEN can be used to extend the
previous cycle when required.
Bidirectional Data I/O lines. As inputs, they feed into an on-chip data register that
is triggered by the rising edge of CLK. As outputs, they deliver the data contained
in the memory location specified by A[16:0] during the previous clock rise of the
read cycle. The direction of the pins is controlled by OE and the internal control
logic. When OE is asserted LOW, the pins can behave as outputs. When HIGH,
DQ[31:0] are placed in a three-state condition. The outputs are automatically
three-stated during the data portion of a write sequence, during the first clock when
emerging from a deselected state, and when the device is deselected, regardless
of the state of OE.
Bidirectional Data Parity I/O lines. Functionally, these signals are identical to
DQ[31:0]. During write sequences, DP0 is controlled by BWS0, DP1 is controlled by
BWS1, DP2 is controlled by BWS2, and DP3 is controlled by BWS3.
Mode Input. Selects the burst order of the device. Tied HIGH selects the inter-
leaved burst order. Pulled LOW selects the linear burst order. MODE should not
change states during operation. When left floating MODE will default HIGH, to an
interleaved burst order.
Power supply inputs to the core of the device. Should be connected to 3.3V power
supply.
Power supply for the I/O circuitry. Should be connected to a 3.3V power supply.
Document #: 38-05246 Rev. **
Page 3 of 14










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WCSN0436V1P128Kx36 Pipelined SRAMWeida Semiconductor
Weida Semiconductor

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