PDF WCSS0232V1P Data sheet ( Hoja de datos )

Número de pieza	WCSS0232V1P
Descripción	64K x 32 Synchronous-Pipelined Cache RAM
Fabricantes	Weida Semiconductor
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No Preview Available ! WCSS0232V1P Revised: February 7, 2002 WCSS0232V1P 64K x 32 Synchronous-Pipelined Cache RAM Features • Supports 133-MHz bus for Pentium® and PowerPC™ operations with zero wait states • Fully registered inputs and outputs for pipelined operation • 64K x 32 common I/O architecture • Single 3.3V power supply • Fast clock-to-output times www.DataSheet4—U.4c.o2mns (for 133-MHz device) — 5.5 ns (for 100-MHz device) — 7.0 ns (for 75-MHz device • User-selectable burst counter supporting Intel® Pentium interleaved or linear burst sequences • Separate processor and controller address strobes • Synchronous self-timed writes • Asynchronous output enable • JEDEC-standard 100 TQFP pinout • “ZZ” Sleep Mode option and Stop Clock option Functional Description The WCSS0232V1P is a 3.3V, 64K by 32 synchronous-pipe- lined cache SRAM designed to support zero wait state sec- ondary cache with minimal glue logic. Logic Block Diagram CLK ADV ADSC ADSP A[15:0] GW BWE BW 3 BW2 16 MODE (A[1:0]) 2 BURST Q0 CE COUNTER CLR Q1 Q ADDRESS CE D REGISTER 14 D DQ[31:24] Q BYTEWRITE REGISTERS D DQ[23:16] Q BYTEWRITE REGISTERS BW1 BW0 CE1 CE2 CE3 D DQ[15:8] Q BYTEWRITE REGISTERS D DQ[7:0] Q BYTEWRITE REGISTERS D CE ENABLE REGISTER Q CLK All synchronous inputs pass through input registers controlled by the rising edge of the clock. All data outputs pass through output registers controlled by the rising edge of the clock. Max- imum access delay from the clock rise is 4.2 ns (133-MHz device). The WCSS0232V1P supports either the interleaved burst se- quence used by the Intel Pentium processor or a linear burst sequence used by processors such as the PowerPC. The burst sequence is selected through the MODE pin. Accesses can be initiated by asserting either the Processor Address Strobe (ADSP) or the Controller Address Strobe (ADSC) at clock rise. Address advancement through the burst sequence is controlled by the ADV input. A 2-bit on-chip wraparound burst counter captures the first address in a burst sequence and automatically increments the address for the rest of the burst access. Byte write operations are qualified with the four Byte Write Select (BW[3:0]) inputs. A Global Write Enable (GW) overrides all byte write inputs and writes data to all four bytes. All writes are conducted with on-chip synchronous self-timed write cir- cuitry. Three synchronous Chip Selects (CE1, CE2, CE3) and an asynchronous Output Enable (OE) provide for easy bank se- lection and output three-state control. In order to provide prop- er data during depth expansion, OE is masked during the first clock of a read cycle when emerging from a deselected state. 14 16 64KX32 MEMORY ARRAY 32 32 DQ ENABLE DELAY REGISTER CLK OUTPUT REGISTERS CLK INPUT REGISTERS CLK OE ZZ SLEEP CONTROL DQ[31:0] Intel and Pentium are registered trademarks of Intel Corporation. PowerPC is a trademark of IBM Corporation. February 7, 2002 1 page : WCSS0232V1P Linear Burst Sequence First Address A[1:0] 00 01 10 11 Second Address A[1:0] 01 10 11 00 Third Address A[1:0] 10 11 00 01 Fourth Address A[1:0] 11 00 01 10 Sleep Mode The ZZ input pin is an asynchronous input. Asserting ZZ plac- es the SRAM in a power conservation “sleep” mode. Two clock cycles are required to enter into or exit from this “sleep” mode. While in this mode, data integrity is guaranteed. Accesses pending when entering the “sleep” mode are not considered valid nor is the completion of the operation guaranteed. The device must be deselected prior to entering the “sleep” mode. CE1, CE2, CE3, ADSP, and ADSC must remain inactive for the duration of tZZREC after the ZZ input returns LOW. ZZ Mode Electrical Characteristics www.DataSheet4UP.caormameter Description Test Conditions IDDZZ Snooze mode standby current ZZ > VDD − 0.2V tZZS Device operation to ZZ > VDD − 0.2V ZZ tZZREC ZZ recovery time ZZ < 0.2V Cycle Descriptions[1,2,3] Min 2tCYC Max 3 2tCYC Unit mA ns ns Next Cycle Unselected Add. Used None ZZ L CE3 CE2 CE1 ADSP ADSC ADV OE XX1 X 0 XX Unselected None L 1X0 0 X XX Unselected None LX0 0 0 X XX Unselected None L1X0 1 0 XX Unselected None LX00 1 0 XX Begin Read External L010 0 X XX Begin Read External L010 1 0 XX Continue Read Next LXXX 1 1 01 Continue Read Next LXXX 1 1 00 Continue Read Next LXX1 X 1 0 1 Continue Read Next LXX1 X 1 00 Suspend Read Current LXXX 1 1 11 Suspend Read Current LXXX 1 1 10 Suspend Read Current LXX1 X 1 11 Suspend Read Current LXX1 X 1 10 Begin Write Current LXXX 1 1 1X Begin Write Current LXX1 X 1 1X Begin Write External L010 1 0 XX Continue Write Next LXXX 1 1 0X Continue Write Next LXX1 X 1 0X Suspend Write Current LXXX 1 1 1X Suspend Write Current LXX1 X 1 1X ZZ “sleep” None HXXX X X XX Notes: 1. X=”Don't Care”, 1=HIGH, 0=LOW. 2. Write is defined by BWE, BW[3:0], and GW. See Write Cycle Descriptions table. 3. The DQ pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock. DQ Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z DQ Hi-Z DQ Hi-Z DQ Hi-Z DQ Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Write X X X X X X read read read read read read read read read write write write write write write write X 5 5 Page : WCSS0232V1P Switching Waveforms (continued) Read/Write Cycle Timing[14,15,16, 17] CLK tADS ADSP www.DataSheet4U.com ADSC ADV Single Read tCYC Single Write tCH tADH tADS tADVS tCL tADH Burst Read Unselected Pipelined Read ADSP ignored with CE1 inactive tAS ADD RD1 tADVH WD2 tAH GW tWS tWH WE CE1 tCES tCEH RD3 tWS tWH CE1 masks ADSP CE2 tCES CE3 tCES OE Data- In/Out tCEH tCEH tDOE tOEHZ tOELZ tCO 1O1aaut 2a In See Note 17 2a Out tDS tDH 3a Out 3b Out = DON’T CARE = UNDEFINED tDOH 3c 3d Out Out TCHZ Note: 17. Data bus is driven by SRAM, but data is not guaranteed. 11 11 Page

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