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PDF SC4603 Data sheet ( Hoja de datos )

Número de pieza SC4603
Descripción High Efficiency Synchronous Buck
Fabricantes Semtech Corporation 
Logotipo Semtech Corporation Logotipo



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POWER MANAGEMENT
Description
The SC4603 is a voltage mode step down (buck) regula-
tor controller that provides accurate high efficiency power
conversion from input supply range 2.25V to 5.5V. A high
level of integration reduces external component count
and makes it suitable for low voltage applications where
cost, size and efficiency are critical.
The SC4603 drives external complementary power
www.DataMtShhOeeeSlt4oFUwE.Tcsosm;idPe.-cThhaennuesleonofthheighhigshidseidPe-cahnadnnNe-cl hManOnSeFlEoTns
eliminates the need for an external charge pump and
simplifies the high side gate driver. Non-overlap protec-
tion is provided for the gate drive signals to prevent shoot
through of the MOSFET pair. The voltage drop across the
P-channel MOSFET during its conduction is sensed for
lossless short circuit current limiting.
A low power sleep mode can be achieved by forcing the
SYNC/SLEEP pin below 0.8V. A synchronous mode of op-
eration is activated as the SYNC/SLEEP pin is driven by
an external clock. The quiescent supply current in sleep
mode is typically lower than 10µA. A 1.7ms soft start is
internally provided to prevent output voltage overshoot
during start-up. A 100% maximum duty cycle allows the
SC4603 to operate as a low dropout regulator in the
event of a low battery condition.
SC4603
Very Low Input, MHz Operation,
High Efficiency Synchronous Buck
Features
‹ BICMOS voltage mode PWM controller
‹ 2.25V to 5.5V Input voltage range
‹ Output voltages as low as 0.5V
‹ Sleep mode (Icc = 10µA typ)
‹ Lossless adjustable overcurrent protection
‹ Combination pulse by pulse & hiccup mode current
limit
‹ High efficiency synchronous switching
‹ 0% to 100% Duty cycle range
‹ Synchronization to external clock
‹ Asynchronous start-up
‹ 1MHz frequency of operation
‹ 10-Pin MSOP surface mount package
Applications
‹ Distributed power architecture
‹ Servers/workstations
‹ Local microprocessor core power supplies
‹ DSP and I/O power supplies
‹ Battery powered applications
‹ Telecommunication equipment
‹ Data processing applications
The SC4603 is an ideal choice for 3.3V, 5V or other low
input supply systems. It’s available in 10 pin MSOP
package.
Typical Application Circuit
RT
34.8k
C3 4.7u
C1 150p
R1 C2
20k 1n
R 15
1
U1
5 FS
1 VCC
2 SYNC
3 COMP
4 VSENSE
R3
ISET
PDRV
PH ASE
NDRV
GN D
6
10
7
9
8
SC4603
C 14
33n
M1
R6
1. 0
M2
R5
1.0
Vin = 2.25V ~ 5.5V
C10 C11
C12 C13
22u 22u
22u 22u
L1 Vout = 1.5V (as low as 0.5V * ) /6A
2. 3u
C7
150u
C4
22u
C9
1. 2n
R7
14k
R8
806
* External components can be modified to provide a Vout as low as 0.5V.
R9
6.98k
Revision: May 5, 2004
1
www.semtech.com

1 page




SC4603 pdf
SC4603
POWER MANAGEMENT
Pin Configuration
Top View
Ordering Information
Part Number(1)
Device
SC4603IMSTRT(2)
MSOP-10
Notes:
(1) Only available in tape and reel packaging. A reel
contains 2500 devices.
(2) Lead free product.
www.DataSheet4U.com
(10 Pin MSOP)
Pin Descriptions
VCC: Positive supply rail for the IC. Bypass this pin to
GND with a 0.1 to 4.7µF low ESL/ESR ceramic capaci-
tor.
GND: All voltages are measured with respect to this pin.
All bypass and timing capacitors connected to GND should
have leads as short and direct as possible.
FS: An external resistor connected with FS pin sets the
clock frequency.
SYNC/SLEEP: The oscillator frequency of SC4603 is
set by FS when SYNC/SLEEP is pulled and held above
2V. Its synchronous mode operation is activated as the
SYNC/SLEEP is driven by an external clock. The oscilla-
tor and PWM are designed to provide practical operation
to 1MHz when synchronized. Sleep mode is invoked if
SYNC/SLEEP is pulled and held below 0.8V which can be
accomplished by an external gate or transistor. The
Sleepmode supply current is 10µA typical.
VSENSE: This pin is the inverting input of the voltage
amplifier and serves as the output voltage feedback point
for the Buck converter. It senses the output voltage through
an external divider.
PHASE, ISET: PHASE input is connected to the junction
between the two external power MOSFET transistors. The
voltage drop across the upper P-channel device is moni-
tored by PHASE and ISET during PFET conduction and
forms the current limit comparator and logic that sets
the PWM latch and terminates the PFET output pulse
once excessive voltage drop across the PFET is detected.
The controller stops switching and goes through a soft
start sequence once the converter output voltage drops
below 70% its nominal voltage. This prevents excess
power dissipation in the PMOSFET during a short circuit.
The current limit threshold is set by the external resistor
between VCC and ISET. The internal 50µA current source
has a positive temperature coefficient that can compen-
sate PMOSFET Rdson variation due to its junction tem-
perature change.
PDRV, NDRV: The PWM circuitry provides complemen-
tary drive signals to the output stages. The Cross con-
duction of the external MOSFETs is prevented by moni-
toring the voltage on the P-channel and N-channel driver
pins in conjunction with a time delay optimized for FET
turn-off characteristics.
COMP: This is the output of the voltage amplifier. The
voltage at this output is connected to the inverting input
of the PWM comparator. A lead-lag network around the
voltage amplifier compensates for the two pole LC filter
characteristic inherent to voltage mode control and is
required in order to optimize the dynamic performance
of the voltage mode control loop.
2004 Semtech Corp.
5
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5 Page





SC4603 arduino
SC4603
POWER MANAGEMENT
Applications Information - (Cont.)
For a low voltage and high output current application such
as the 3.3V/1.5V@6A case, the conduction loss is often
dominant and selecting low RDS(ON) MOSFETs will notice-
ably improve the efficiency of the converter even though
they give higher switching losses.
The gate charge loss portion of the top/bottom MOSFET’s
total power loss is derived from the SC4603. This gate
charge loss is based on certain operating conditions
www.Data(Sfhs,eeVtG4AUTE.c,oamnd IO).
The thermal estimations have to be done for both
MOSFETs to make sure that their junction temperatures
do not exceed their thermal ratings according to their
total power losses PTOTAL, ambient temperature TA and their
thermal resistances RθJA as follows:
TJ(max)
<
TA
+
PTOTAL
R θJA
Loop Compensation Design:
For example, if
VREF @ 2.25V =
VCC = 2.25V, the reference voltage,
V @ 3.3V
REF
+
Vref @ 3.3V
100
Change @2.25V VCC 3.3V =
Internal Reference
500
+
500
100
0.1
2.25 3.3
=
500.5(mV )
C2
C1
5 FS
1 VCC
2 SYNC
3 COMP
4 VSENSE
ISET
PDRV
PHASE
NDRV
GND
6
10
7
9
8
SC4603
R1
L1
C9
R8
Vout
C4 R
R7
R9
For a DC/DC converter, it is usually required that the
converter has a loop gain of a high cross-over frequency
for fast load response, high DC and low frequency gain
for low steady state error, and enough phase margin for
its operating stability. Often one can not have all these
properties at the same time. The purpose of the loop
compensation is to arrange the poles and zeros of the
compensation network to meet the requirements for a
specific application.
The SC4603 has an internal error amplifier and requires
the compensation network to connect among the COMP
pin and VSENSE pin, GND, and the output as shown in
Figure 3. The compensation network includes C1, C2,
R1, R7, R8 and C9. R9 is used to program the output
voltage according to:
VOUT
=
0.5
(1
+
R
R
7
9
)
As indicated in Internal Reference Change section, the
internal reference voltage (measured at VSENSE pin)
changes slightly if the input voltage of the SC4603 is
away from 3.3V.
Figure 3. Compensation network provides 3 poles and
2 zeros.
For voltage mode step down applications as shown in
Figure 3, the power stage transfer function is:
1+
s
1
G VD (s)
=
VIN
1+
s
RC
L1
R
+
C4
s2L1C4
Where:
R = load resistance and
RC = C4’s ESR.
The compensation network will have the characteristic
as follows:
1+ s 1+ s
GCOMP (s) =
ωI
s
1+
ωZ1
s
1+
ωZ2
s
ωP1 ωP2
2004 Semtech Corp.
11
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