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PDF W83977EG Data sheet ( Hoja de datos )

Número de pieza W83977EG
Descripción WINBOND ISA I/O
Fabricantes Winbond 
Logotipo Winbond Logotipo



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No Preview Available ! W83977EG Hoja de datos, Descripción, Manual

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WINBOND
ISA I/O
W83977EF
W83977EG

1 page




W83977EG pdf
W83977EF-AW/W83977EG-AW
9.
www.DataSheet4U.com
10.
11.
12.
13.
8.6 OnNow / Security Keyboard and Mouse Wake-Up ...................................................... 73
8.6.1 Keyboard Wake-Up Function........................................................................................73
8.6.2 Keyboard Password Wake-Up Function .......................................................................73
8.6.3 Mouse Wake-Up Function ............................................................................................73
GENERAL PURPOSE I/O......................................................................................................... 74
9.1 Basic I/O functions........................................................................................................ 76
9.2 Alternate I/O Functions ................................................................................................. 78
9.2.1 Interrupt Steering..........................................................................................................78
9.2.2 Watch Dog Timer Output..............................................................................................78
9.2.3 Power LED ...................................................................................................................79
9.2.4 General Purpose Address Decoder..............................................................................79
PLUG AND PLAY CONFIGURATION ...................................................................................... 80
10.1 Compatible PnP............................................................................................................ 80
10.1.1 Extended Function Registers........................................................................................80
10.1.2 Extended Functions Enable Registers (EFERs) ...........................................................81
10.1.3 Extended Function Index Registers (EFIRs), Extended Function Data
Registers(EFDRs) .......................................................................................................................81
10.2 Configuration Sequence ............................................................................................... 81
10.2.1 Enter the extended function mode................................................................................81
10.2.2 Configurate the configuration registers.........................................................................82
10.2.3 Exit the extended function mode ..................................................................................82
10.2.4 Software programming example...................................................................................82
ACPI REGISTERS FEATURES................................................................................................ 83
CONFIGURATION REGISTER ................................................................................................ 84
12.1 Chip (Global) Control Register ..................................................................................... 84
12.2 Logical Device 0 (FDC)................................................................................................. 90
12.3 Logical Device 1 (Parallel Port) .................................................................................... 94
12.4 Logical Device 2 (UART A)¢) ....................................................................................... 95
12.5 Logical Device 3 (UART B)........................................................................................... 95
12.6 Logical Device 5 (KBC)................................................................................................. 97
12.7 Logical Device 7 (GP I/O Port I) ................................................................................... 98
12.8 Logical Device 8 (GP I/O Port II) ................................................................................ 101
12.9 Logical Device A (ACPI) ............................................................................................. 105
SPECIFICATIONS .................................................................................................................. 112
13.1 Absolute Maximum Ratings ........................................................................................ 112
13.2 DC CHARACTERISTICS............................................................................................ 112
13.3 AC Characteristics ...................................................................................................... 116
13.3.1 FDC: Data rate = 1 MB, 500 KB, 300 KB, 250 KB/sec. ..............................................116
13.3.2 UART/Parallel Port .....................................................................................................118
13.3.3 Parallel Port Mode Parameters...................................................................................118
13.3.4 EPP Data or Address Read Cycle Timing Parameters...............................................119
-IV-

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W83977EG arduino
W83977EF-AW/W83977EG-AW
4. PIN DESCRIPTION
Note: Please refer to Section 11.2 DC CHARACTERISTICS for details.
I/O6t - TTL level bi-directional pin with 6 mA source-sink capability
I/O8t - TTL level bi-directional pin with 8 mA source-sink capability
I/O8 - CMOS level bi-directional pin with 8 mA source-sink capability
I/O12t - TTL level bi-directional pin with 12 mA source-sink capability
I/O12 - CMOS level bi-directional pin with 12 mA source-sink capability
I/O16u - CMOS level bi-directional pin with 16 mA source-sink capability with internal pull-up resistor
www.DataSheet4U.comI/OD16u - CMOS level bi-directional pin open drain output with 16 mA sink capability with internal pull-up resistor
I/O24t - TTL level bi-directional pin with 24 mA source-sink capability
OUT8t - TTL level output pin with 8 mA source-sink capability
OUT12t - TTL level output pin with 12 mA source-sink capability
OD12 - Open-drain output pin with 12 mA sink capability
OD24 - Open-drain output pin with 24 mA sink capability
INt - TTL level input pin
INc - CMOS level input pin
INcu
- CMOS level input pin with internal pull-up resitor
INcs
- CMOS level Schmitt-triggered input pin
INts - TTL level Schmitt-triggered input pin
INtsu - TTL level Schmitt-triggered input pin with internal pull-up resistor
4.1 Host Interface
SYMBOL
A0A10
A11-A14
A15
D0D5
D6D7
IOR#
IOW#
AEN
PIN
74-84
86-89
91
109-114
116-117
105
106
107
IOCHRDY
108
MR 118
DACK0#
GP16
(WDTO)
P15
119
I/O
INt
INt
INt
I/O12t
I/O12t
INts
INts
INts
OD24
INts
INtsu
I/O12t
I/O12t
FUNCTION
System address bus bits 0-10
System address bus bits 11-14
System address bus bit 15
System data bus bits 0-5
System data bus bits 6-7
CPU I/O read signal
CPU I/O write signal
System address bus enable
In EPP Mode, this pin is the IO Channel Ready output to
extend the host read/write cycle.
Master Reset; Active high; MR is low during normal
operations.
DMA Channel 0 Acknowledge signal. (CR2C bit 5_4 = 00,
default)
General purpose I/O port 1bit 6. (CR2C bit 5_4 = 01)
Alternate function from GP16: Watch dog timer output
KBC P15 I/O port. (CR2C bit 5_4 = 10)
Publication Release Date: Apr. 2006
-9- Revision 1.2

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