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PDF 74AHCT2G32 Data sheet ( Hoja de datos )
| Número de pieza | 74AHCT2G32 | |
| Descripción | Dual 2-input OR gate | |
| Fabricantes | NXP Semiconductors | |
| Logotipo |  |
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74AHC2G32; 74AHCT2G32
Dual 2-input OR gate
Rev. 3 — 14 May 2013
Product data sheet
1. General description
The 74AHC2G32; 74AHCT2G32 is a high-speed Si-gate CMOS device.
The 74AHC2G32; 74AHCT2G32 provides two 2-input OR gates.
2. Features and benefits
Symmetrical output impedance
High noise immunity
ESD protection:
HBM JESD22-A114E exceeds 2000 V
MM JESD22-A115-A exceeds 200 V
CDM JESD22-C101C exceeds 1000 V
Low power dissipation
Balanced propagation delays
Multiple package options
Specified from 40 C to +85 C and from 40 C to +125 C
3. Ordering information
Table 1. Ordering information
Type number
Package
Temperature range Name
74AHC2G32DP 40 C to +125 C TSSOP8
74AHCT2G32DP
74AHC2G32DC 40 C to +125 C VSSOP8
74AHCT2G32DC
74AHC2G32GD 40 C to +125 C XSON8
74AHCT2G32GD
Description
Version
plastic thin shrink small outline package; 8 leads; body SOT505-2
width 3 mm; lead length 0.5 mm
plastic very thin shrink small outline package; 8 leads; SOT765-1
body width 2.3 mm
plastic extremely thin small outline package; no leads; SOT996-2
8 terminals; body 3 2 0.5 mm
1 page  
NXP Semiconductors
74AHC2G32; 74AHCT2G32
Dual 2-input OR gate
Table 7. Static characteristics …continued
Voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions
74AHCT2G32
VIH HIGH-level VCC = 4.5 V to 5.5 V
input voltage
VIL LOW-level VCC = 4.5 V to 5.5 V
input voltage
VOH
VOL
II
ICC
ICC
CI
HIGH-level VI = VIH or VIL; VCC = 4.5 V
output voltage IO = 50 A
IO = 8.0 mA
LOW-level VI = VIH or VIL; VCC = 4.5 V
output voltage IO = 50 A
IO = 8.0 mA
input leakage VI = 5.5 V or GND;
current
VCC = 0 V to 5.5 V
supply current VI = VCC or GND; IO = 0 A;
VCC = 5.5 V
additional
per input pin; VI = 3.4 V;
supply current other inputs at VCC or GND;
IO = 0 A; VCC = 5.5 V
input
capacitance
25 C
40 C to +85 C 40 C to +125 C Unit
Min Typ Max Min Max Min
Max
2.0 -
--
- 2.0
0.8 -
-
0.8
2.0 -
- 0.8
V
V
4.4 4.5 -
3.94 -
-
4.4 -
3.8 -
4.4 -
3.70 -
- 0 0.1 -
- - 0.36 -
- - 0.1 -
- - 1.0 -
- - 1.35 -
0.1 -
0.44 -
1.0 -
10 -
1.5 -
0.1
0.55
2.0
40
1.5
V
V
V
V
A
A
mA
- 1.5 10 - 10 - 10 pF
11. Dynamic characteristics
Table 8. Dynamic characteristics
GND = 0 V; for test circuit see Figure 7.
Symbol Parameter Conditions
25 C
40 C to +85 C 40 C to +125 C Unit
Min Typ Max Min Max Min Max
74AHC2G32
tpd propagation nA, nB to nY; see Figure 6 [1]
delay
VCC = 3.0 V to 3.6 V
[2]
CL = 15 pF
- 4.4 7.9 1.0 9.5 1.0 10.0 ns
CL = 50 pF
- 6.3 11.4 1.0
13.0
1.0
14.5 ns
VCC = 4.5 V to 5.5 V
[3]
CL = 15 pF
- 3.2 5.5 1.0
6.5
1.0
7.0 ns
CL = 50 pF
- 4.6 7.5 1.0
8.5
1.0
9.5 ns
CPD power
per buffer;
[4] - 16 -
-
-
-
- pF
dissipation CL = 50 pF; fi = 1 MHz;
capacitance VI = GND to VCC
74AHC_AHCT2G32
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 3 — 14 May 2013
© NXP B.V. 2013. All rights reserved.
5 of 14
5 Page 
NXP Semiconductors
74AHC2G32; 74AHCT2G32
Dual 2-input OR gate
14. Abbreviations
Table 11. Abbreviations
Acronym
Description
CDM
Charged Device Model
CMOS
Complementary Metal-Oxide Semiconductor
DUT
Device Under Test
ESD
ElectroStatic Discharge
HBM
Human Body Model
MM Machine Model
TTL Transistor-Transistor Logic
15. Revision history
Table 12. Revision history
Document ID
Release date Data sheet status
Change notice Supersedes
74AHC_AHCT2G32 v.3
Modifications:
20130514
Product data sheet
-
74AHC_AHCT2G32 v.2
• For type number 74AHC2G32GD and 74AHCT2G32GD XSON8U has changed to XSON8.
74AHC_AHCT2G32 v.2
Modifications:
20090120
Product data sheet
-
74AHC_AHCT2G32 v.1
• The format of this data sheet has been redesigned to comply with the new identity
guidelines of NXP Semiconductors.
• Legal texts have been adapted to the new company name where appropriate.
• Added type number 74AHC2G32GD and 74AHCT2G32GD (XSON8U package).
74AHC_AHCT2G32 v.1 20040223
Product specification
-
-
74AHC_AHCT2G32
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 3 — 14 May 2013
© NXP B.V. 2013. All rights reserved.
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