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Número de pieza | PI74ALVCH16646 | |
Descripción | 16-Bit Bus Transceiver and Register | |
Fabricantes | Pericom Semiconductor Corporation | |
Logotipo | ||
Hay una vista previa y un enlace de descarga de PI74ALVCH16646 (archivo pdf) en la parte inferior de esta página. Total 6 Páginas | ||
No Preview Available ! PI74ALVCH16646
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Product Features
16-Bit Bus Transceiver and Register
with 3-STATE Outputs
Product Description
• PI74ALVCH16646 is designed for low voltage operation
• VCC = 2.3V to 3.6V
• Hysteresis on all inputs
• Typical VOLP (Output Ground Bounce)
< 0.8V at VCC = 3.3V, TA = 25°C
www.DataS•heTeyt4pUic.caolmVOHV (Output VOH Undershoot)
< 2.0V at VCC = 3.3V, TA = 25°C
• Bus Hold retains last active bus state during 3-STATE,
eliminating the need for external pullup resistors
• Industrial operation at 40°C to +85°C
• Packages available:
56-pin 240 mil wide plastic TSSOP (A)
56-pin 300 mil wide plastic SSOP (V)
Pericom Semiconductors PI74ALVCH series of logic circuits are
produced in the Companys advanced 0.5 micron CMOS
technology, achieving industry leading speed.
The PI74ALVCH16646 is a 16-bit bus transceiver and register
designed for 2.3V to 3.6V VCC operation. It can be used as two
8-bit transceivers or one 16-bit transceiver. Data on the A or B bus
is clocked into the registers on the low-to-high transition of the
appropriate Clock (CLKAB or CLKBA) input. Four fundamental
bus-management functions can be performed.
Output Enable (OE) and Direction Control (DIR) inputs are provided
to control the transceiver functions. In the transceiver mode, data
present at the high-impedance port may be stored in either register
or in both. The Select Control (SAB and SBA) inputs can multiplex
stored and real-time (transparent mode) data. Circuitry used for
Select Control eliminates the typical decoding glitch that occurs in
a multiplexer during the transition between stored and real-time
data. DIR determines which bus receives data when OE is LOW.
In the isolation mode (OE HIGH), A data may be stored in one
register and/or B data may be stored in the other register.
When an output function is disabled, the input function is still
enabled and may be used to store and transmit data. Only one of the
two buses, A or B, can be driven at a time.
To ensure the high-impedance state during power up or power
down, OE should be tied to VCC through a pullup resistor; the
minimum value of the resistor is determined by the current-sinking
capability of the driver.
Logic Block Diagram
Active bus-hold circuitry is provided to hold unused or floating
data inputs at a valid logic level.
1 PS8102A 10/07/98
1 page PI74ALVCH16646
16-Bit Bus Transceiver and Register
1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123w45i6t7h89031-2S34T56A78T90E121O23u45t6p78u9t01s2
DC Electrical Characteristics-Continued (Over the Operating Range, TA = 40°C to +85°C, VCC = 3.3V ±10%)
Parameters Description
Test Conditions(1)
Min. Typ.(2) Max. Units
IIN
Input Current
VIN = VCC or GND, VCC = 3.6V
±5
VIN = 0.7V, VCC = 2.3V
45
IIN (HOLD)
www.DataSheet4U.com
IOZ
ICC
DICC
CI
CO
Input
Hold
Current
Output Current (3-STATE Outputs)
Supply Current
Supply Current per Input
@ TTL HIGH
Control Inputs
Data Inputs
Outputs
VIN = 1.7V, VCC = 2.3V
VIN = 0.8V, VCC = 3.0V
VIN = 2.0V, VCC = 3.0V
VIN = 0 to 3.6V, VCC = 3.6V
VOUT = VCC or GND, VCC = 3.6V
VCC = 3.6V, IOUT = 0mA,
VIN = GND or VCC
VCC = 3.0V to 3.6V
One Input at VCC - 0.6V
Other Inputs at VCC or GND
VIN = VCC or GND, VCC = 3.3V
VO = VCC or GND, VCC = 3.3V
-45
75
-75
±500
±10
40
mA
750
3
6 pF
7
Notes:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at VCC = 3.3V, +25°C ambient and maximum loading.
3. Unused Control Inputs must be held HIGH or LOW to prevent them from floating.
Timing Requirements
Parameters
FCLOCK
tW
tSU
tH
Description
Conditions(1)
VCC = 2.5V ±0.2V
Min.(2) Max.
Clock Frequency
0 150
Pulse Duration
CLKAB or CLKBA
HIGH or LOW
Setup Time
A Before CLKAB or
B Before CLKBA
CL = 50pF
RL = 500W
3.3
1.6
Hold Time
A After CLKAB or
B After CLKBA
0.6
VCC = 2.7V
Min.(2) Max.
0 150
VCC = 3.3V ±0.3V
Min.(2) Max.
0 150
Units
MHz
3.3 3.3
1.7 1.4 ns
0.4 0.7
5 PS8102A 10/07/98
5 Page |
Páginas | Total 6 Páginas | |
PDF Descargar | [ Datasheet PI74ALVCH16646.PDF ] |
Número de pieza | Descripción | Fabricantes |
PI74ALVCH16646 | 16-Bit Bus Transceiver and Register | Pericom Semiconductor Corporation |
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